I2C
2
13.2 I C AC Electrical Specifications
2
Table 46 provides the AC timing parameters for the I C interfaces.
2
Table 46. I C AC Electrical Specifications
1
Parameter
Symbol
Min
Max
Unit
Notes
SCL clock frequency
f
0
400
—
kHz
μs
—
4
I2C
Low period of the SCL clock
t
t
1.3
0.6
0.6
0.6
I2CL
High period of the SCL clock
—
μs
4
I2CH
Setup time for a repeated START condition
t
—
μs
4
I2SVKH
Hold time (repeated) START condition (after this period,
the first clock pulse is generated)
t
—
μs
4
I2SXKL
Data setup time
t
100
—
ns
4
2
I2DVKH
Data input hold time:
t
μs
I2DXKL
I2OVKL
CBUS compatible masters
—
0
—
—
2
I C bus devices
Data output delay time:
t
—
0.6
0.9
—
—
—
—
μs
μs
V
3
Set-up time for STOP condition
t
—
—
—
I2PVKH
Bus free time between a STOP and START condition
t
1.3
I2KHDX
Noise margin at the LOW level for each connected device
(including hysteresis)
V
0.1 × OV
NL
DD
DD
Noise margin at the HIGH level for each connected
device (including hysteresis)
V
0.2 × OV
—
V
—
NH
Notes:
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
2
inputs and t
for outputs. For example, t
symbolizes I C timing (I2)
(first two letters of functional block)(reference)(state)(signal)(state)
I2DVKH
with respect to the time data input signals (D) reach the valid state (V) relative to the t clock reference (K) going to the high
I2C
2
(H) state or setup time. Also, t
symbolizes I C timing (I2) for the time that the data with respect to the start condition
clock reference (K) going to the low (L) state or hold time. Also, t
I2SXKL
2
(S) went invalid (X) relative to the t
symbolizes I C
I2C
I2PVKH
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t clock
I2C
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. As a transmitter, the MPC8548E provides a delay time of at least 300 ns for the SDA signal (refer to the V (min) of the SCL
IH
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition.
2
When MPC8548E acts as the I C bus master while transmitting, MPC8548E drives both SCL and SDA. As long as the load
on SCL and SDA are balanced, MPC8548E would not cause unintended generation of Start or Stop condition. Therefore,
the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required
for MPC8548E as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure
2
2
both the desired I C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I C SCL clock
frequency is 400 kHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is programmed with its default setting of
0x10 (decimal 16):
2
I C source clock frequency
FDR bit setting
333 MHz 266 MHz
200 MHz
0x26
512
133 MHz
0x00
384
0x2A
896
0x05
704
Actual FDR divider selected
Actual I C SCL frequency generated 371 kHz
For the detail of I C frequency calculation, refer to Freescale Application Note AN2919, Determining the I C Frequency
Divider Ratio for SCL. Note that the I C source clock frequency is half of the CCB clock frequency for MPC8548E.
2
378 kHz
390 kHz
346 kHz
2
2
2
3. The maximum t
has only to be met if the device does not stretch the LOW period (t
) of the SCL signal.
I2CL
I2DXKL
4. Guaranteed by design.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
55
FREESCALE [ Freescale ]
