PCI/PCI-X
14.2 PCI/PCI-X AC Electrical Specifications
This section describes the general AC timing parameters of the PCI/PCI-X bus. Note that the clock
reference CLK is represented by SYSCLK when the PCI controller is configured for asynchronous mode
and by PCIn_CLK when it is configured for asynchronous mode.
Table 48 provides the PCI AC timing specifications at 66 MHz.
Table 48. PCI AC Timing Specifications at 66 MHz
1
Parameter
Symbol
Min
Max
Unit
Notes
CLK to output valid
t
t
t
—
2.0
6.0
—
14
—
—
—
50
—
ns
ns
2, 3
PCKHOV
PCKHOX
PCKHOZ
Output hold from CLK
2, 10
CLK to output high impedance
Input setup to CLK
—
ns
2, 4, 11
2, 5, 10
2, 5, 10
6, 7, 11
7, 11
t
3.0
ns
PCIVKH
PCIXKH
PCRVRH
PCRHRX
Input hold from CLK
t
0
ns
9
REQ64 to HRESET setup time
t
t
10 × t
clocks
ns
SYS
HRESET to REQ64 hold time
HRESET high to first FRAME assertion
Notes:
0
t
10
clocks
8, 11
PCRHFV
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes PCI/PCI-X
(first two letters of functional block)(reference)(state)(signal)(state)
PCIVKH
timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock, t
, reference
SYS
(K) going to the high (H) state or setup time. Also, t
symbolizes PCI/PCI-X timing (PC) with respect to the time hard
PCRHFV
reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. All PCI signals are measured from OV /2 of the rising edge of SYSCLK or PCI_CLKn to 0.4 × OV of the signal in question
DD
DD
for 3.3-V PCI signaling levels.
4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
5. Input timings are measured at the pin.
6. The timing parameter t
indicates the minimum and maximum CLK cycle times for the various specified frequencies. The
SYS
system clock period must be kept within the minimum and maximum defined ranges. For values see Section 19, “Clocking.”
7. The setup and hold time is with respect to the rising edge of HRESET.
8. The timing parameter t
Specifications.
is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus
PCRHFV
9. The reset assertion timing requirement for HRESET is 100 μs.
10.Guaranteed by characterization.
11.Guaranteed by design.
Figure 35 provides the AC test load for PCI and PCI-X.
Output
Z = 50 Ω
0
LV /2
DD
R = 50 Ω
L
Figure 35. PCI/PCI-X AC Test Load
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
57
FREESCALE [ Freescale ]
