Programmable Interrupt Controller
Internal Launch/Capture Clock
T1
T2
T3
T4
LCLK
t
t
LBKLOX1
LBKLOV1
GPCM Mode Output Signals:
LCS[0:7]/LWE
t
LBKLOZ1
GPCM Mode Input Signal:
LGTA
t
LBIVKL2
t
LBIXKL2
UPM Mode Input Signal:
LUPWAIT
t
LBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBIXKH1
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 28. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 8 or 16 (PLL Bypass Mode)
11 Programmable Interrupt Controller
In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed
polarity), it must remain the assertion for at least 3 system clocks (SYSCLK periods).
12 JTAG
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of
the MPC8548E.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
51
FREESCALE [ Freescale ]
