PCI/PCI-X
Table 49. PCI-X AC Timing Specifications at 66 MHz (continued)
Parameter
Symbol
Min
Max
Unit
Notes
6, 11
HRESET to PCI-X initialization pattern hold time
t
0
50
ns
PCRHIX
Notes:
1. See the timing measurement conditions in the PCI-X 1.0a Specification.
2. Minimum times are measured at the package pin (not the test point). Maximum times are measured with the test point and
load circuit.
3. Setup time for point-to-point signals applies to REQ and GNT only. All other signals are bused.
4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
5. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time.
6. Maximum value is also limited by delay to the first transaction (time for HRESET high to first configuration access, t
).
PCRHFV
The PCI-X initialization pattern control signals after the rising edge of HRESET must be negated no later than two clocks
before the first FRAME and must be floated no later than one clock before FRAME is asserted.
7. A PCI-X device is permitted to have the minimum values shown for t
and t
only in PCI-X mode. In conventional
CYC
PCKHOV
mode, the device must meet the requirements specified in PCI 2.2 for the appropriate clock frequency.
8. Device must meet this specification independent of how many outputs switch simultaneously.
9. The timing parameter t
is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI-X 1.0a Specification.
PCRHFV
10.Guaranteed by characterization.
11.Guaranteed by design.
Table 50 provides the PCI-X AC timing specifications at 133 MHz.
Note that the maximum PCI-X frequency in synchronous mode is 110 MHz.
Table 50. PCI-X AC Timing Specifications at 133 MHz
Parameter
SYSCLK to signal valid delay
Symbol
Min
Max
Unit
Notes
t
—
0.7
—
3.8
—
7
ns
ns
1, 2, 3, 7, 8
1, 11
PCKHOV
Output hold from SYSCLK
t
PCKHOX
PCKHOZ
SYSCLK to output high impedance
Input setup time to SYSCLK
t
ns
1, 4, 8, 12
3, 5, 9, 11
11
t
1.2
0.5
10
0
—
—
—
50
—
—
ns
PCIVKH
PCIXKH
PCRVRH
PCRHRX
Input hold time from SYSCLK
t
ns
REQ64 to HRESET setup time
HRESET to REQ64 hold time
t
clocks
ns
12
t
12
HRESET high to first FRAME assertion
PCI-X initialization pattern to HRESET setup time
t
10
10
clocks
clocks
10, 12
12
PCRHFV
t
PCIVRH
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
59
FREESCALE [ Freescale ]
