PCI/PCI-X
Figure 36 shows the PCI/PCI-X input AC timing conditions.
CLK
t
PCIVKH
t
PCIXKH
Input
Figure 36. PCI/PCI-X Input AC Timing Measurement Conditions
Figure 37 shows the PCI/PCI-X output AC timing conditions.
CLK
t
PCKHOV
Output Delay
t
PCKHOZ
High-Impedance
Output
Figure 37. PCI/PCI-X Output AC Timing Measurement Condition
Table 49 provides the PCI-X AC timing specifications at 66 MHz.
Table 49. PCI-X AC Timing Specifications at 66 MHz
Parameter
SYSCLK to signal valid delay
Symbol
Min
Max
Unit
Notes
t
—
0.7
—
3.8
—
7
ns
ns
1, 2, 3, 7, 8
1, 10
1, 4, 8, 11
3, 5
PCKHOV
Output hold from SYSCLK
t
PCKHOX
PCKHOZ
SYSCLK to output high impedance
Input setup time to SYSCLK
t
ns
t
1.7
0.5
10
0
—
—
—
50
—
—
ns
PCIVKH
PCIXKH
PCRVRH
PCRHRX
Input hold time from SYSCLK
t
ns
10
REQ64 to HRESET setup time
HRESET to REQ64 hold time
t
t
clocks
ns
11
11
HRESET high to first FRAME assertion
PCI-X initialization pattern to HRESET setup time
t
t
10
10
clocks
clocks
9, 11
11
PCRHFV
PCIVRH
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
58
FREESCALE [ Freescale ]
