JTAG
1
Table 44. JTAG AC Timing Specifications (Independent of SYSCLK) (continued)
2
Parameter
Symbol
Min
Max
Unit
Notes
JTAG external clock to output high impedance:
ns
Boundary-scan data
TDO
t
t
3
3
19
9
5, 6
JTKLDZ
JTKLOZ
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
to the midpoint of the signal in question.
TCLK
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 29).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes JTAG device
(first two letters of functional block)(reference)(state)(signal)(state)
JTDVKH
timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
clock reference (K)
JTG
going to the high (H) state or setup time. Also, t
symbolizes JTAG timing (JT) with respect to the time data input signals
JTDXKH
(D) went invalid (X) relative to the t
clock reference (K) going to the high (H) state. Note that, in general, the clock reference
JTG
symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
.
TCLK
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design.
.
TCLK
Figure 29 provides the AC test load for TDO and the boundary-scan outputs.
Output
OV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 29. AC Test Load for the JTAG Interface
Figure 30 provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
t
VM
VM
t
JTGR
JTKHKL
t
t
JTGF
JTG
VM = Midpoint Voltage (OV /2)
DD
Figure 30. JTAG Clock Input Timing Diagram
Figure 31 provides the TRST timing diagram.
TRST
VM
VM
t
TRST
VM = Midpoint Voltage (OV /2)
DD
Figure 31. TRST Timing Diagram
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
53
FREESCALE [ Freescale ]
