Local Bus
Internal Launch/Capture Clock
T1
T3
LCLK
t
t
LBKLOX1
LBKLOV1
GPCM Mode Output Signals:
LCS[0:7]/LWE
t
LBKLOZ1
GPCM Mode Input Signal:
LGTA
t
LBIVKL2
t
LBIXKL2
UPM Mode Input Signal:
LUPWAIT
t
LBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBIXKH1
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Bypass Mode)
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
49