Local Bus
Figure 23 through Figure 28 show the local bus signals.
LSYNC_IN
t
LBIXKH1
t
t
LBIVKH1
LBIVKH2
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBIXKH2
Input Signal:
LGTA
LUPWAIT
t
LBKHOZ1
LBKHOX1
t
t
t
t
t
LBKHOV1
Output Signals:
LA[27:31]/LBCTL/LBCKE/LOE/
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
t
LBKHOZ2
LBKHOX2
LBKHOV2
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOZ2
LBKHOX2
t
LBKHOV3
Output (Address) Signal:
LAD[0:31]
t
LBOTOT
t
LBKHOV4
LALE
Figure 23. Local Bus Signals (PLL Enabled)
Table 42 describes the timing parameters of the local bus interface at BV = 3.3 V with PLL disabled.
DD
Table 42. Local Bus Timing Parameters—PLL Bypassed
1
Parameter
Symbol
Min
Max
Unit
Notes
Local bus cycle time
Local bus duty cycle
t
12
43
—
57
ns
%
2
—
LBK
t
t
LBKH/ LBK
Internal launch/capture clock to LCLK delay
t
2.3
6.2
6.1
–1.8
–1.3
1.5
—
4.4
—
ns
ns
ns
ns
ns
ns
ns
ns
8
LBKHKT
Input setup to local bus clock (except LGTA/LUPWAIT)
LGTA/LUPWAIT input setup to local bus clock
t
4, 5
4, 5
4, 5
4, 5
6
LBIVKH1
t
—
LBIVKL2
Input hold from local bus clock (except LGTA/LUPWAIT)
LGTA/LUPWAIT input hold from local bus clock
t
—
LBIXKH1
t
—
LBIXKL2
LALE output transition to LAD/LDP output transition (LATCH hold time)
Local bus clock to output valid (except LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
t
—
LBOTOT
t
t
–0.3
–0.1
—
LBKLOV1
LBKLOV2
—
4
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
45
FREESCALE [ Freescale ]
