Local Bus
Internal Launch/Capture Clock
LCLK[n]
t
LBKHKT
t
LBIVKH1
t
LBIXKH1
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBIVKL2
Input Signal:
LGTA
t
LBIXKL2
LUPWAIT
t
LBKLOV1
t
LBKLOZ1
LBKLOZ2
t
LBKLOX1
Output Signals:
LA[27:31]/LBCTL/LBCKE/LOE/
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
t
t
LBKLOV2
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
t
t
LBKLOX2
LBKLOV3
Output (Address) Signal:
LAD[0:31]
t
t
LBKLOV4
LBOTOT
LALE
Figure 24. Local Bus Signals (PLL Bypass Mode)
NOTE
In PLL bypass mode, LCLK[n] is the inverted version of the internal clock
with the delay of tLBKHKT. In this mode, signals are launched at the rising edge
of the internal clock and are captured at falling edge of the internal clock
with the exception of LGTA/LUPWAIT (which is captured on the rising
edge of the internal clock).
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
47
FREESCALE [ Freescale ]
