Local Bus
Table 42. Local Bus Timing Parameters—PLL Bypassed (continued)
1
Parameter
Symbol
Min
Max
Unit
Notes
Local bus clock to address valid for LAD
t
t
t
—
—
0
0
ns
ns
ns
ns
ns
ns
4
4
4
4
7
7
LBKLOV3
LBKLOV4
LBKLOX1
Local bus clock to LALE assertion
Output hold from local bus clock (except LAD/LDP and LALE)
Output hold from local bus clock for LAD/LDP
Local bus clock to output high Impedance (except LAD/LDP and LALE)
Local bus clock to output high impedance for LAD/LDP
Notes:
–3.7
–3.7
—
—
—
0.2
0.2
t
LBKLOX2
LBKLOZ1
LBKLOZ2
t
t
—
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes local bus
(first two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock reference (K) goes high (H), in this case for
LBK
clock one (1). Also, t
symbolizes local bus timing (LB) for the t
clock reference (K) to go high (H), with respect to
LBKHOX
LBK
the output (O) going invalid (X) or output hold time.
2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus
clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes LCLK
by t
.
LBKHKT
3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BV /2.
DD
4. All signals are measured from BV /2 of the rising edge of local bus clock for PLL bypass mode to 0.4 × BV of the signal
DD
DD
in question for 3.3-V signaling levels.
5. Input timings are measured at the pin.
6. The value of t
is the measurement of the minimum time between the negation of LALE and any change in LAD.
LBOTOT
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
8. Guaranteed by characterization.
9. Guaranteed by design.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
46
Freescale Semiconductor
FREESCALE [ Freescale ]
