MPC8543EVUAQG 参数 Datasheet PDF下载

Local Bus

Table 41. Local Bus Timing Parameters (BV

DD

= 2.5 V)—PLL Enabled (continued)

Parameter

Local bus clock to output high Impedance (except LAD/LDP and LALE)

Local bus clock to output high impedance for LAD/LDP

Symbol

1

t

LBKHOZ1

t

LBKHOZ2

Min

—

—

Max

2.6

2.6

Unit

ns

ns

Notes

5

5

Notes:

1. The symbols used for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)(reference)(state)

for

inputs and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. For example, t

LBIXKH1

symbolizes local bus

timing (LB) for the input (I) to go invalid (X) with respect to the time the t

LBK

clock reference (K) goes high (H), in this case for

clock one (1). Also, t

LBKHOX

symbolizes local bus timing (LB) for the t

LBK

clock reference (K) to go high (H), with respect to

the output (O) going invalid (X) or output hold time.

2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.

3. All signals are measured from BV

DD

/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL

bypass mode to 0.4

×

BV

DD

of the signal in question for 3.3-V signaling levels.

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

6. t

LBOTOT

is a measurement of the minimum time between the negation of LALE and any change in LAD. t

LBOTOT

is

programmed with the LBCR[AHD] parameter.

7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at BV

DD

/2.

8. Guaranteed by design.

provides the AC test load for the local bus.

Output

Z

0

= 50

Ω

R

L

= 50

Ω

BV

DD

/2

Figure 22. Local Bus AC Test Load

NOTE

PLL bypass mode is required when LBIU frequency is at or below 83 MHz.

When LBIU operates above 83 MHz, LBIU PLL is recommended to be

enabled.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6

44

Freescale Semiconductor