Local Bus
Table 40. Local Bus Timing Parameters (BV = 3.3 V)—PLL Enabled (continued)
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1
Parameter
Symbol
Min
Max
Unit
Notes
Local bus clock to output high impedance for LAD/LDP
t
—
2.5
ns
5
LBKHOZ2
Notes:
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes local bus
(first two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock reference (K) goes high (H), in this case for
LBK
clock one (1). Also, t
symbolizes local bus timing (LB) for the t
clock reference (K) to go high (H), with respect to
LBKHOX
LBK
the output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BV /2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
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bypass mode to 0.4 × BV of the signal in question for 3.3-V signaling levels.
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4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
6. t
is a measurement of the minimum time between the negation of LALE and any change in LAD. t
is
LBOTOT
LBOTOT
programmed with the LBCR[AHD] parameter.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BV /2.
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8. Guaranteed by design.
Table 41 describes the timing parameters of the local bus interface at BV = 2.5 V.
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Table 41. Local Bus Timing Parameters (BV = 2.5 V)—PLL Enabled
DD
1
Parameter
Symbol
Min
Max
Unit
Notes
Local bus cycle time
Local bus duty cycle
t
7.5
43
—
12
57
150
—
ns
%
2
—
7, 8
3, 4
3, 4
3, 4
3, 4
6
LBK
t
t
LBKH/ LBK
LCLK[n] skew to LCLK[m] or LSYNC_OUT
t
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LBKSKEW
Input setup to local bus clock (except LGTA/UPWAIT)
LGTA/LUPWAIT input setup to local bus clock
Input hold from local bus clock (except LGTA/LUPWAIT)
LGTA/LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output transition (LATCH hold time)
Local bus clock to output valid (except LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
t
t
t
t
1.9
1.8
1.1
1.1
1.5
—
LBIVKH1
LBIVKH2
LBIXKH1
LBIXKH2
—
—
—
t
—
LBOTOT
t
2.1
2.3
2.4
2.4
—
—
3
LBKHOV1
LBKHOV2
LBKHOV3
LBKHOV4
LBKHOX1
t
t
t
t
—
Local bus clock to address valid for LAD
—
3
Local bus clock to LALE assertion
—
3
Output hold from local bus clock (except LAD/LDP and LALE)
Output hold from local bus clock for LAD/LDP
0.8
0.8
3
t
—
3
LBKHOX2
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
43
FREESCALE [ Freescale ]
