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MPC8543EVUAQG 参数 Datasheet PDF下载

MPC8543EVUAQG图片预览
型号: MPC8543EVUAQG
PDF下载: 下载PDF文件 查看货源
内容描述: 的PowerQUICC ™III集成处理器硬件规格 [PowerQUICC™ III Integrated Processor Hardware Specifications]
分类和应用:
文件页数/大小: 144 页 / 1534 K
品牌: FREESCALE [ Freescale ]
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Local Bus  
Table 39 provides the DC electrical characteristics for the local bus interface operating at  
BV = 2.5 V DC.  
DD  
Table 39. Local Bus DC Electrical Characteristics (2.5 V DC)  
Parameter  
Symbol  
Min  
Max  
Unit  
High-level input voltage  
V
1.70  
–0.3  
BV + 0.3  
V
V
IH  
DD  
Low-level input voltage  
V
I
0.7  
10  
IL  
1
Input current (V  
= 0 V or V = BV  
)
μA  
IN  
IN  
DD  
IH  
I
–15  
IL  
High-level output voltage (BV = min, I = –1 mA)  
V
OH  
2.0  
V
V
DD  
OH  
Low-level output voltage (BV = min, I = 1 mA)  
V
OL  
0.4  
DD  
OL  
Note:  
1. Note that the symbol V , in this case, represents the BV symbol referenced in Table 1 and Table 2.  
IN  
IN  
10.2 Local Bus AC Electrical Specifications  
Table 40 describes the timing parameters of the local bus interface at BV = 3.3 V. For information about  
DD  
the frequency range of local bus, see Section 19.1, “Clock Ranges.”  
Table 40. Local Bus Timing Parameters (BV = 3.3 V)—PLL Enabled  
DD  
1
Parameter  
Symbol  
Min  
Max  
Unit  
Notes  
Local bus cycle time  
Local bus duty cycle  
t
7.5  
43  
12  
57  
150  
ns  
%
2
7, 8  
3, 4  
3, 4  
3, 4  
3, 4  
6
LBK  
t
t
LBKH/ LBK  
LCLK[n] skew to LCLK[m] or LSYNC_OUT  
t
ps  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
LBKSKEW  
Input setup to local bus clock (except LGTA/LUPWAIT)  
LGTA/LUPWAIT input setup to local bus clock  
t
t
t
t
1.8  
1.7  
1.0  
1.0  
1.5  
LBIVKH1  
LBIVKH2  
LBIXKH1  
LBIXKH2  
Input hold from local bus clock (except LGTA/LUPWAIT)  
LGTA/LUPWAIT input hold from local bus clock  
LALE output transition to LAD/LDP output transition (LATCH hold time)  
Local bus clock to output valid (except LAD/LDP and LALE)  
Local bus clock to data valid for LAD/LDP  
t
LBOTOT  
t
2.0  
2.2  
2.3  
2.3  
3
LBKHOV1  
LBKHOV2  
LBKHOV3  
LBKHOV4  
LBKHOX1  
t
t
t
t
Local bus clock to address valid for LAD  
3
Local bus clock to LALE assertion  
3
Output hold from local bus clock (except LAD/LDP and LALE)  
Output hold from local bus clock for LAD/LDP  
0.7  
0.7  
3
t
3
LBKHOX2  
Local bus clock to output high Impedance (except LAD/LDP and LALE)  
t
2.5  
5
LBKHOZ1  
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6  
Freescale Semiconductor  
42  
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