Ethernet Management Interface Electrical Characteristics
Table 36. MII Management DC Electrical Characteristics (continued)
Parameter
Symbol
Min
Max
Unit
1
Input high current (OV = Max, V
= 2.1 V)
I
—
40
—
μA
μA
DD
IN
IH
Input low current (OV = Max, V = 0.5 V)
I
–600
DD
IN
IL
Note:
1. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
9.2
MII Management AC Electrical Specifications
Table 37 provides the MII management AC timing specifications.
Table 37. MII Management AC Timing Specifications
At recommended operating conditions with OVDD is 3.3 V ± 5%.
1
Parameter
MDC frequency
Symbol
Min
Typ
Max
Unit
Notes
f
t
0.72
120.5
32
2.5
—
—
—
—
—
—
—
8.3
1389
—
MHz
ns
2, 3, 4
MDC
MDC period
—
—
5
MDC
MDC clock pulse width high
MDC to MDIO valid
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
t
ns
MDCH
t
t
t
t
16 × t
—
ns
MDKHDV
MDKHDX
MDDVKH
MDDXKH
CCB
(16 × t
× 8) – 3
(16 × t
× 8) + 3
ns
5
ptb_clk
ptb_clk
5
—
ns
—
—
4
0
—
10
10
ns
t
—
—
ns
MDCR
MDC fall time
t
ns
4
MDHF
Notes:
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes management
(first two letters of functional block)(reference)(state)(signal)(state)
MDKHDX
data timing (MD) for the time t
from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
MDC
Also, t
symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
MDDVKH
(V) relative to the t
clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention
MDC
is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the eTSEC system clock speed, which is half of the Platform Frequency (f
). The actual
CCB
ECn_MDC output clock frequency for a specific eTSEC port can be programmed by configuring the MgmtClk bit field of
MPC8548E’s MIIMCFG register, based on the platform (CCB) clock running for the device. The formula is: Platform Frequency
(CCB) ÷ (2 × Frequency Divider determined by MIICFG[MgmtClk] encoding selection). For example, if
MIICFG[MgmtClk] = 000 and the platform (CCB) is currently running at 533 MHz, f
= 533) ÷ (2 × 4 × 8) = 533) ÷ 64 =
MDC
8.3 MHz. That is, for a system running at a particular platform frequency (f
), the ECn_MDC output clock frequency can be
CCB
programmed between maximum f
= f
÷ 64 and minimum f = f
÷ 448. Refer to MPC8572E reference manual’s
MDC
CCB
MDC
CCB
MIIMCFG register section for more detail.3.The maximum ECn_MDC output clock frequency is defined based on the
maximum platform frequency for MPC8548E (533 MHz) divided by 64, while the minimum ECn_MDC output clock frequency
is defined based on the minimum platform frequency for MPC8548E (333 MHz) divided by 448, following the formula
described in Note 2 above.
4. Guaranteed by design.
5. t
is the platform (CCB) clock period.
CCB
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
40
FREESCALE [ Freescale ]
