Ethernet Management Interface Electrical Characteristics
Table 36. MII Management DC Electrical Characteristics (continued)
Parameter
Input high current (OV
DD
= Max, V
IN1
= 2.1 V)
Input low current (OV
DD
= Max, V
IN
= 0.5 V)
Symbol
I
IH
I
IL
Min
—
–600
Max
40
—
Unit
μA
μA
Note:
1. Note that the symbol V
IN
, in this case, represents the OV
IN
symbol referenced in
and
9.2
MII Management AC Electrical Specifications
Table 37. MII Management AC Timing Specifications
provides the MII management AC timing specifications.
At recommended operating conditions with OV
DD
is 3.3 V ± 5%.
Parameter
MDC frequency
MDC period
MDC clock pulse width high
MDC to MDIO valid
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
MDC fall time
Symbol
1
f
MDC
t
MDC
t
MDCH
t
MDKHDV
t
MDKHDX
t
MDDVKH
t
MDDXKH
t
MDCR
t
MDHF
Min
0.72
120.5
32
16
×
t
CCB
(16 × t
ptb_clk
× 8) – 3
5
0
—
—
Typ
2.5
—
—
—
—
—
—
—
Max
8.3
1389
—
—
(16 × t
ptb_clk
× 8) + 3
—
—
10
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Notes
2, 3, 4
—
—
5
5
—
—
4
4
Notes:
1. The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state)(reference)(state)
for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
MDKHDX
symbolizes management
data timing (MD) for the time t
MDC
from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
Also, t
MDDVKH
symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
(V) relative to the t
MDC
clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention
is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the eTSEC system clock speed, which is half of the Platform Frequency (f
CCB
). The actual
ECn_MDC output clock frequency for a specific eTSEC port can be programmed by configuring the MgmtClk bit field of
MPC8548E’s MIIMCFG register, based on the platform (CCB) clock running for the device. The formula is: Platform Frequency
(CCB)
÷
(2 × Frequency Divider determined by MIICFG[MgmtClk] encoding selection). For example, if
MIICFG[MgmtClk] = 000 and the platform (CCB) is currently running at 533 MHz, f
MDC
= 533)
÷
(2 × 4 × 8) = 533)
÷
64 =
8.3 MHz. That is, for a system running at a particular platform frequency (f
CCB
), the ECn_MDC output clock frequency can be
programmed between maximum f
MDC
= f
CCB
÷
64 and minimum f
MDC
= f
CCB
÷
448. Refer to MPC8572E reference manual’s
MIIMCFG register section for more detail.3.The maximum ECn_MDC output clock frequency is defined based on the
maximum platform frequency for MPC8548E (533 MHz) divided by 64, while the minimum ECn_MDC output clock frequency
is defined based on the minimum platform frequency for MPC8548E (333 MHz) divided by 448, following the formula
described in Note 2 above.
4. Guaranteed by design.
5. t
CCB
is the platform (CCB) clock period.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
40
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
