Enhanced Three-Speed Ethernet (eTSEC)
Table 34. RMII Transmit AC Timing Specifications (continued)
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
TSECn_TX_CLK to RMII data TXD[1:0], TX_EN delay
t
1.0
—
10.0
ns
RMTDX
Note:
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes MII transmit
(first two letters of functional block)(reference)(state)(signal)(state)
MTKHDX
timing (MT) for the time t
clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,
MTX
the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.
For example, the subscript of t represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is
MTX
used with the appropriate letter: R (rise) or F (fall).
Figure 18 shows the RMII transmit AC timing diagram.
t
t
RMTR
RMT
TSECn_TX_CLK
t
t
RMTH
RMTF
TXD[1:0]
TX_EN
TX_ER
t
RMTDX
Figure 18. RMII Transmit AC Timing Diagram
8.2.7.2
RMII Receive AC Timing Specifications
Table 35. RMII Receive AC Timing Specifications
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
TSECn_TX_CLK clock period
t
15.0
35
20.0
50
—
25.0
65
ns
%
RMR
TSECn_TX_CLK duty cycle
t
t
RMRH
TSECn_TX_CLK peak-to-peak jitter
t
—
250
2.0
2.0
—
ps
ns
ns
ns
ns
RMRJ
Rise time TSECn_TX_CLK(20%–80%)
Fall time TSECn_TX_CLK (80%–20%)
1.0
1.0
4.0
2.0
—
RMRR
t
—
RMRF
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge
t
—
RMRDV
t
—
—
RMRDX
Note:
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes MII receive
(first two letters of functional block)(reference)(state)(signal)(state)
MRDVKH
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
clock reference (K)
MRX
going to the high (H) state or setup time. Also, t
symbolizes MII receive timing (GR) with respect to the time data input
MRDXKL
signals (D) went invalid (X) relative to the t
clock reference (K) going to the low (L) state or hold time. Note that, in general,
MRX
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of t represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
MRX
with the appropriate letter: R (rise) or F (fall).
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
38
FREESCALE [ Freescale ]
