Input Clocks
4.3
eTSEC Gigabit Reference Clock Timing
Table 6 provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for
the MPC8548E.
Table 6. EC_GTX_CLK125 AC Timing Specifications
Parameter/Condition
EC_GTX_CLK125 frequency
Symbol
Min
Typ
Max
Unit
Notes
f
t
—
—
—
125
8
—
—
MHz
ns
—
G125
G125
EC_GTX_CLK125 cycle time
EC_GTX_CLK125 rise and fall time
t
, t
—
ns
1
G125R G125F
L/TVDD = 2.5 V
L/TVDD = 3.3 V
0.75
1.0
EC_GTX_CLK125 duty cycle
t
/t
—
%
2, 3
G125H G125
GMII, TBI
1000Base-T for RGMII, RTBI
45
47
55
53
Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for L/TV = 2.5 V, and from 0.6 and 2.7 V for
DD
L/TV = 3.3 V.
DD
2. Timing is guaranteed by design and characterization.
3. EC_GTX_CLK125 is used to generate the GTX clock TSECn_GTX_CLK for the eTSEC transmitter with 2% degradation.
EC_GTX_CLK125 duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle generated
by the TSECn_ GTX_CLK. See Section 8.2.6, “RGMII and RTBI AC Timing Specifications,” for duty cycle for 10Base-T and
100Base-T reference clock.
4.4
PCI/PCI-X Reference Clock Timing
When the PCI/PCI-X controller is configured for asynchronous operation, the reference clock for the
PCI/PCI-x controller is not the SYSCLK input, but instead the PCIn_CLK. Table 7 provides the
PCI/PCI-X reference clock AC timing specifications for the MPC8548E.
Table 7. PCIn_CLK AC Timing Specifications
At recommended operating conditions (see Table 2) with OV = 3.3 V ± 165 mV.
DD
Parameter/Condition
PCIn_CLK frequency
Symbol
Min
Typ
Max
Unit
Notes
f
t
16
7.5
0.6
40
—
—
133
60
MHz
ns
—
—
PCICLK
PCIn_CLK cycle time
PCIn_CLK rise and fall time
PCIn_CLK duty cycle
Notes:
PCICLK
t
, t
1.0
—
2.1
60
ns
1, 2
2
PCIKH PCIKL
t
/t
%
PCIKHKL PCICLK
1. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.
2. Timing is guaranteed by design and characterization.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
16