Electrical Characteristics
Table 2. Recommended Operating Conditions (continued)
Characteristic
Junction temperature range
Symbol
Tj
Recommended
Value
0 to 105
Unit
°C
Notes
—
Notes:
1. This voltage is the input to the filter discussed in
and not necessarily the voltage
at the AV
DD
pin, which may be reduced from V
DD
by the filter.
2.
Caution:
MV
IN
must not exceed GV
DD
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3.
Caution:
OV
IN
must not exceed OV
DD
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4.
Caution:
L/TV
IN
must not exceed L/TV
DD
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
shows the undershoot and overshoot voltages at the interfaces of this device.
B/G/L/O/TV
DD
+ 20%
B/G/L/O/TV
DD
+ 5%
V
IH
B/G/L/O/TV
DD
GND
GND – 0.3 V
V
IL
GND – 0.7 V
Not to Exceed 10%
of t
CLOCK1
Notes:
1. t
CLOCK
refers to the clock period associated with the respective interface:
For I
2
C and JTAG, t
CLOCK
references SYSCLK.
For DDR, t
CLOCK
references MCLK.
For eTSEC, t
CLOCK
references EC_GTX_CLK125.
For LBIU, t
CLOCK
references LCLK.
For PCI, t
CLOCK
references PCIn_CLK or SYSCLK.
For SerDes, t
CLOCK
references SD_REF_CLK.
2. Please note that with the PCI overshoot allowed (as specified above), the device
does not fully comply with the maximum AC ratings and device protection
guideline outlined in the PCI rev. 2.2 standard (section 4.2.2.3).
Figure 2. Overshoot/Undershoot Voltage for GV
DD
/OV
DD
/LV
DD
/BV
DD
/TV
DD
The core voltage must always be provided at nominal 1.1 V. Voltage to the processor interface I/Os are
provided through separate sets of supply pins and must be provided at the voltages shown in
The
input voltage threshold scales with respect to the associated I/O supply voltage. OV
DD
and LV
DD
based
receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR
SDRAM interface uses a single-ended differential receiver referenced the externally supplied MV
REF
signal (nominally set to GV
DD
/2) as is appropriate for the SSTL2 electrical signaling standard.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
12
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
