Electrical Characteristics
Table 2. Recommended Operating Conditions (continued)
Recommended
Value
Characteristic
Symbol
Unit
Notes
Junction temperature range
Tj
0 to 105
°C
—
Notes:
1. This voltage is the input to the filter discussed in Section 21.2, “PLL Power Supply Filtering,” and not necessarily the voltage
at the AV pin, which may be reduced from V by the filter.
DD
DD
2. Caution: MV must not exceed GV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
IN
DD
power-on reset and power-down sequences.
3. Caution: OV must not exceed OV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
IN
DD
power-on reset and power-down sequences.
4. Caution: L/TV must not exceed L/TV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
IN
DD
power-on reset and power-down sequences.
Figure 2 shows the undershoot and overshoot voltages at the interfaces of this device.
B/G/L/O/TV + 20%
DD
B/G/L/O/TV + 5%
DD
B/G/L/O/TV
V
DD
IH
GND
GND – 0.3 V
V
IL
GND – 0.7 V
Not to Exceed 10%
1
of t
CLOCK
Notes:
1. t
refers to the clock period associated with the respective interface:
CLOCK
2
For I C and JTAG, t
For DDR, t
For eTSEC, t
references SYSCLK.
CLOCK
references MCLK.
CLOCK
CLOCK
references EC_GTX_CLK125.
For LBIU, t
CLOCK
For SerDes, t
references LCLK.
CLOCK
For PCI, t
references PCIn_CLK or SYSCLK.
references SD_REF_CLK.
CLOCK
2. Please note that with the PCI overshoot allowed (as specified above), the device
does not fully comply with the maximum AC ratings and device protection
guideline outlined in the PCI rev. 2.2 standard (section 4.2.2.3).
Figure 2. Overshoot/Undershoot Voltage for GV /OV /LV /BV /TV
DD
DD
DD
DD
DD
The core voltage must always be provided at nominal 1.1 V. Voltage to the processor interface I/Os are
provided through separate sets of supply pins and must be provided at the voltages shown in Table 2. The
input voltage threshold scales with respect to the associated I/O supply voltage. OV and LV based
DD
DD
receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR
SDRAM interface uses a single-ended differential receiver referenced the externally supplied MV
REF
signal (nominally set to GV /2) as is appropriate for the SSTL2 electrical signaling standard.
DD
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
12
Freescale Semiconductor
FREESCALE [ Freescale ]
