Electrical Characteristics
2.1.3
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
Table 3. Output Drive Capability
Programmable
Supply
Driver Type
Output Impedance
Notes
Voltage
(Ω)
Local bus interface utilities signals
25
25
BV = 3.3 V
1
DD
BV = 2.5 V
DD
45(default)
45(default)
BV = 3.3 V
DD
BV = 2.5 V
DD
PCI signals
25
OV = 3.3 V
2
DD
45(default)
DDR signal
18
GV = 2.5 V
3
3
DD
36 (half strength mode)
DDR2 signal
18
GV = 1.8 V
DD
36 (half strength mode)
TSEC/10/100 signals
45
45
L/TV = 2.5/3.3 V
—
—
—
DD
DUART, system control, JTAG
OV = 3.3 V
DD
I2C
150
OV = 3.3 V
DD
Notes:
1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.
2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset.
3. The drive strength of the DDR interface in half-strength mode is at T = 105°C and at GV (min).
j
DD
2.2
Power Sequencing
The device requires its power rails to be applied in a specific sequence in order to ensure proper device
operation. These requirements are as follows for power-up:
1. V , AV _n, BV , LV , OV , SV , TV , XV
DD
DD
DD
DD
DD
DD
DD
DD
2. GV
DD
All supplies must be at their stable values within 50 ms.
NOTE
Items on the same line have no ordering requirement with respect to one
another. Items on separate lines must be ordered sequentially such that
voltage rails on a previous step must reach 90% of their value before the
voltage rails on the current step reach 10% of theirs.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
13
FREESCALE [ Freescale ]
