欢迎访问ic37.com |
会员登录 免费注册
发布采购

MPC8543EVUAQG 参数 Datasheet PDF下载

MPC8543EVUAQG图片预览
型号: MPC8543EVUAQG
PDF下载: 下载PDF文件 查看货源
内容描述: 的PowerQUICC ™III集成处理器硬件规格 [PowerQUICC™ III Integrated Processor Hardware Specifications]
分类和应用:
文件页数/大小: 144 页 / 1534 K
品牌: FREESCALE [ Freescale ]
 浏览型号MPC8543EVUAQG的Datasheet PDF文件第14页浏览型号MPC8543EVUAQG的Datasheet PDF文件第15页浏览型号MPC8543EVUAQG的Datasheet PDF文件第16页浏览型号MPC8543EVUAQG的Datasheet PDF文件第17页浏览型号MPC8543EVUAQG的Datasheet PDF文件第19页浏览型号MPC8543EVUAQG的Datasheet PDF文件第20页浏览型号MPC8543EVUAQG的Datasheet PDF文件第21页浏览型号MPC8543EVUAQG的Datasheet PDF文件第22页  
RESET Initialization  
5 RESET Initialization  
This section describes the AC electrical specifications for the RESET initialization timing requirements of  
the MPC8548E. Table 8 provides the RESET initialization AC timing specifications for the DDR SDRAM  
component(s).  
Table 8. RESET Initialization Timing Specifications  
Parameter/Condition  
Required assertion time of HRESET  
Min  
Max  
Unit  
Notes  
100  
3
μs  
1
Minimum assertion time for SRESET  
SYSCLKs  
μs  
PLL input setup time with stable SYSCLK before HRESET negation  
100  
4
1
Input setup time for POR configs (other than PLL config) with respect to  
negation of HRESET  
SYSCLKs  
Input hold time for all POR configs (including PLL config) with respect to  
negation of HRESET  
2
5
SYSCLKs  
SYSCLKs  
1
1
Maximum valid-to-high impedance time for actively driven POR configs with  
respect to negation of HRESET  
Note:  
1. SYSCLK is the primary clock input for the MPC8548E.  
Table 9 provides the PLL lock times.  
Table 9. PLL Lock Times  
Parameter/Condition  
Min  
Max  
Unit  
Core and platform PLL lock times  
Local bus PLL lock time  
100  
50  
μs  
μs  
μs  
PCI/PCI-X bus PLL lock time  
50  
5.1  
Power-On Ramp Rate  
This section describes the AC electrical specifications for the power-on ramp rate requirements.  
Controlling the maximum power-on ramp rate is required to avoid falsely triggering the ESD circuitry.  
Table 10 provides the power supply ramp rate specifications.  
Table 10. Power Supply Ramp Rate  
Parameter  
Required ramp rate for MVREF  
Min  
Max  
Unit  
Notes  
3500  
4000  
V/s  
V/s  
1
Required ramp rate for VDD  
1, 2  
Note:  
1. Maximum ramp rate from 200 to 500 mV is most critical as this range may falsely trigger the ESD circuitry.  
2. VDD itself is not vulnerable to false ESD triggering; however, as per Section 21.2, “PLL Power Supply Filtering,the  
recommended AVDD_CORE, AVDD_PLAT, AVDD_LBIU, AVDD_PCI1 and AVDD_PCI2 filters are all connected to VDD.  
Their ramp rates should be equal to or less than the VDD ramp rate.  
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6  
18  
Freescale Semiconductor  
 复制成功!