RESET Initialization
5
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8548E.
provides the RESET initialization AC timing specifications for the DDR SDRAM
component(s).
Table 8. RESET Initialization Timing Specifications
Parameter/Condition
Required assertion time of HRESET
Minimum assertion time for SRESET
PLL input setup time with stable SYSCLK before HRESET negation
Input setup time for POR configs (other than PLL config) with respect to
negation of HRESET
Input hold time for all POR configs (including PLL config) with respect to
negation of HRESET
Maximum valid-to-high impedance time for actively driven POR configs with
respect to negation of HRESET
Note:
1. SYSCLK is the primary clock input for the MPC8548E.
Min
100
3
100
4
2
—
Max
—
—
—
—
—
5
Unit
μs
SYSCLKs
μs
SYSCLKs
SYSCLKs
SYSCLKs
Notes
—
1
—
1
1
1
provides the PLL lock times.
Table 9. PLL Lock Times
Parameter/Condition
Core and platform PLL lock times
Local bus PLL lock time
PCI/PCI-X bus PLL lock time
Min
—
—
—
Max
100
50
50
Unit
μs
μs
μs
5.1
Power-On Ramp Rate
This section describes the AC electrical specifications for the power-on ramp rate requirements.
Controlling the maximum power-on ramp rate is required to avoid falsely triggering the ESD circuitry.
provides the power supply ramp rate specifications.
Table 10. Power Supply Ramp Rate
Parameter
Required ramp rate for MVREF
Required ramp rate for VDD
Min
—
—
Max
3500
4000
Unit
V/s
V/s
Notes
1
1, 2
Note:
1. Maximum ramp rate from 200 to 500 mV is most critical as this range may falsely trigger the ESD circuitry.
2. VDD itself is not vulnerable to false ESD triggering; however, as per
the
recommended AVDD_CORE, AVDD_PLAT, AVDD_LBIU, AVDD_PCI1 and AVDD_PCI2 filters are all connected to VDD.
Their ramp rates should be equal to or less than the VDD ramp rate.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
18
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
