Power Characteristics
NOTE
In order to guarantee MCKE low during power-up, the above sequencing for
GV
DD
is required. If there is no concern about any of the DDR signals being
in an indeterminate state during power-up, then the sequencing for GV
DD
is
not required.
NOTE
From a system standpoint, if any of the I/O power supplies ramp prior to the
V
DD
core supply, the I/Os associated with that I/O supply may drive a logic
one or zero during power-up, and extra current may be drawn by the device.
3
Power Characteristics
Table 4. MPC8548E Power Dissipation
CCB Frequency
1
400
Core Frequency
800
1000
1200
500
533
1500
1333
SLEEP
2
2.7
2.7
2.7
11.5
6.2
Typical-65
3
4.6
5.0
5.4
13.6
7.9
Typical-105
4
7.5
7.9
8.3
16.5
10.8
Maximum
5
8.1
8.5
8.9
18.6
12.8
W
W
Unit
W
W
The estimated typical power dissipation for the core complex bus (CCB) versus the core frequency for this
family of PowerQUICC III devices is shown in
Notes:
1. CCB frequency is the SoC platform frequency, which corresponds to the DDR data rate.
2. SLEEP is based on V
DD
= 1.1 V, T
j
= 65°C.
3. Typical-65 is based on V
DD
= 1.1 V, T
j
= 65°C, running Dhrystone.
4. Typical-105 is based on V
DD
= 1.1 V, T
j
= 105°C, running Dhrystone.
5. Maximum is based on V
DD
= 1.1 V, T
j
= 105°C, running a smoke test.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
14
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
