Power Characteristics
NOTE
In order to guarantee MCKE low during power-up, the above sequencing for
GV is required. If there is no concern about any of the DDR signals being
DD
in an indeterminate state during power-up, then the sequencing for GV is
DD
not required.
NOTE
From a system standpoint, if any of the I/O power supplies ramp prior to the
V
core supply, the I/Os associated with that I/O supply may drive a logic
DD
one or zero during power-up, and extra current may be drawn by the device.
3 Power Characteristics
The estimated typical power dissipation for the core complex bus (CCB) versus the core frequency for this
family of PowerQUICC III devices is shown in Table 4.
Table 4. MPC8548E Power Dissipation
1
2
3
4
5
CCB Frequency
Core Frequency
SLEEP
Typical-65
Typical-105
Maximum
Unit
400
800
2.7
2.7
4.6
5.0
7.5
7.9
8.1
8.5
W
W
1000
1200
1500
1333
2.7
5.4
8.3
8.9
500
533
11.5
6.2
13.6
7.9
16.5
10.8
18.6
12.8
W
W
Notes:
1. CCB frequency is the SoC platform frequency, which corresponds to the DDR data rate.
2. SLEEP is based on V = 1.1 V, T = 65°C.
DD
j
3. Typical-65 is based on V = 1.1 V, T = 65°C, running Dhrystone.
DD
j
4. Typical-105 is based on V = 1.1 V, T = 105°C, running Dhrystone.
DD
j
5. Maximum is based on V = 1.1 V, T = 105°C, running a smoke test.
DD
j
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
14
FREESCALE [ Freescale ]
