System Design Information
Table 81. Package Thermal Characteristics for FC-PBGA (continued)
Characteristic
JEDEC Board
Symbol
Value
Unit
Notes
Die junction-to-case
N/A
R
0.8
°C/W
4
JC
θ
Notes:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1). The cold plate temperature is used for the case temperature, measured value includes the thermal resistance of the
interface layer.
20.3 Heat Sink Solution
Every system application has different conditions that the thermal management solution must solve. As
such, providing a recommended heat sink has not been found to be very useful. When a heat sink is chosen,
give special consideration to the mounting technique. Mounting the heat sink to the printed-circuit board
is the recommended procedure using a maximum of 10 lbs force (45 Newtons) perpendicular to the
package and board. Clipping the heat sink to the package is not recommended.
21 System Design Information
This section provides electrical design recommendations for successful application of the MPC8548E.
21.1 System Clocking
This device includes five PLLs, as follows:
1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The
frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio
configuration bits as described in Section 19.2, “CCB/SYSCLK PLL Ratio.”
2. The e500 core PLL generates the core clock as a slave to the platform clock. The frequency ratio
between the e500 core clock and the platform clock is selected using the e500 PLL ratio
configuration bits as described in Section 19.3, “e500 Core PLL Ratio.”
3. The PCI PLL generates the clocking for the PCI bus.
4. The local bus PLL generates the clock for the local bus.
5. There is a PLL for the SerDes block.
21.2 PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins
(AV _PLAT, AV _CORE, AV _PCI, AV _LBIU, and AV _SRDS, respectively). The AV
DD
DD
DD
DD
DD
DD
level should always be equivalent to V , and preferably these voltages will be derived directly from V
DD
DD
through a low frequency filter scheme such as the following.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
128
Freescale Semiconductor
FREESCALE [ Freescale ]
