System Design Information
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits per PLL power supply as illustrated in Figure 56, one to each of the
AV pins. By providing independent filters to each PLL the opportunity to cause noise injection from
DD
one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV pin being supplied to minimize
DD
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of the footprint, without the inductance of vias.
DD
Figure 56 through Figure 58 shows the PLL power supply filter circuits.
150 Ω
V
V
V
AV _PLAT
DD
DD
DD
DD
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
GND
Figure 56. PLL Power Supply Filter Circuit with PLAT Pins
180 Ω
AV _CORE
DD
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
GND
Figure 57. PLL Power Supply Filter Circuit with CORE Pins
10 Ω
AV _PCI/AV _LBIU
DD
DD
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
GND
Figure 58. PLL Power Supply Filter Circuit with PCI/LBIU Pins
The AV _SRDS signal provides power for the analog portions of the SerDes PLL. To ensure stability of
DD
the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in
following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the
AV _SRDS ball to ensure it filters out as much noise as possible. The ground connection should be near
DD
the AV _SRDS ball. The 0.003-µF capacitor is closest to the ball, followed by the two 2.2 µF capacitors,
DD
and finally the 1 Ω resistor to the board supply plane. The capacitors are connected from AV _SRDS to
DD
the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces
should be kept short, wide and direct.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
129
FREESCALE [ Freescale ]
