System Design Information
directly below the chip supply and ground connections. Where the board does not have blind vias,
these capacitors should be placed in a ring around the device as close to the supply and ground
connections as possible.
•
•
Second, there should be a 1-µF ceramic chip capacitor from each SerDes supply (SV and
DD
XV ) to the board ground plane on each side of the device. This should be done for all SerDes
DD
supplies.
Third, between the device and any SerDes voltage regulator there should be a 10-µF, low
equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT
tantalum chip capacitor. This should be done for all SerDes supplies.
21.5 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. All unused active low inputs should be tied to V , TV , BV , OV , GV , and LV , as
DD
DD
DD
DD
DD
DD
required. All unused active high inputs should be connected to GND. All NC (no-connect) signals must
remain unconnected. Power and ground connections must be made to all external V , TV , BV
,
DD
DD
DD
OV , GV , LV , and GND pins of the device.
DD
DD
DD
21.6 Pull-Up and Pull-Down Resistor Requirements
The MPC8548E requires weak pull-up resistors (2–10 kΩ is recommended) on open drain type pins
2
including I C pins and PIC (interrupt) pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in Figure 62. Care must be taken to ensure that these pins are maintained at a valid deasserted
state under normal operating conditions as most have asynchronous behavior and spurious assertion will
give unpredictable results.
The following pins must not be pulled down during power-on reset: TSEC3_TXD[3], HRESET_REQ,
TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The DMA_DACK[0:1], and TEST_SEL/
TEST_SEL pins must be set to a proper state during POR configuration. Refer to the pinlist table of the
individual device for more details
Refer to the PCI 2.2 specification for all pull ups required for PCI.
21.7 Output Buffer DC Impedance
The MPC8548E drivers are characterized over process, voltage, and temperature. For all buses, the driver
2
is a push-pull single-ended driver type (open drain for I C).
To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to OV
0
DD
or GND. Then, the value of each resistor is varied until the pad voltage is OV /2 (see Figure 60). The
DD
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and R is trimmed until the voltage at the pad equals
P
OV /2. R then becomes the resistance of the pull-up devices. R and R are designed to be close to each
DD
P
P
N
other in value. Then, Z = (R + R )/2.
0
P
N
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
131
FREESCALE [ Freescale ]
