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MPC8543EVUAQG 参数 Datasheet PDF下载

MPC8543EVUAQG图片预览
型号: MPC8543EVUAQG
PDF下载: 下载PDF文件 查看货源
内容描述: 的PowerQUICC ™III集成处理器硬件规格 [PowerQUICC™ III Integrated Processor Hardware Specifications]
分类和应用:
文件页数/大小: 144 页 / 1534 K
品牌: FREESCALE [ Freescale ]
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Clocking  
Table 73. Processor Core Clocking Specifications (MPC8543E)  
Maximum Processor Core Frequency  
Characteristic  
800 MHz  
1000 MHz  
Unit  
Notes  
Min  
Max  
Min  
800  
Max  
e500 core processor frequency  
800  
800  
1000  
MHz  
1, 2  
Notes:  
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK  
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating  
frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,and Section 19.3, “e500 Core PLL Ratio,for ratio settings.  
2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.  
Table 74. Memory Bus Clocking Specifications (MPC8548E and MPC8547E)  
Maximum Processor Core Frequency  
Characteristic  
1000, 1200, 1333 MHz  
Unit  
Notes  
Min  
166  
Max  
Memory bus clock speed  
Notes:  
266  
MHz  
1, 2  
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting  
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum  
operating frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,and Section 19.3, “e500 Core PLL Ratio,for ratio  
settings.  
2. The memory bus speed is half of the DDR/DDR2 data rate, hence, half of the platform clock frequency.  
Table 75. Memory Bus Clocking Specifications (MPC8545E)  
Maximum Processor Core Frequency  
Characteristic  
800, 1000, 1200 MHz  
Unit  
Notes  
Min  
166  
Max  
Memory bus clock speed  
Notes:  
200  
MHz  
1, 2  
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting  
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum  
operating frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,and Section 19.3, “e500 Core PLL Ratio,for ratio  
settings.  
2. The memory bus speed is half of the DDR/DDR2 data rate, hence, half of the platform clock frequency.  
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6  
124  
Freescale Semiconductor  
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