Clocking
Table 73. Processor Core Clocking Specifications (MPC8543E)
Maximum Processor Core Frequency
Characteristic
Min
e500 core processor frequency
800
800 MHz
Max
800
1000 MHz
Min
800
Max
1000
MHz
1, 2
Unit
Notes
Notes:
1.
Caution:
The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to
and
for ratio settings.
2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.
Table 74. Memory Bus Clocking Specifications (MPC8548E and MPC8547E)
Maximum Processor Core Frequency
Characteristic
1000, 1200, 1333 MHz
Min
Memory bus clock speed
166
Max
266
MHz
1, 2
Unit
Notes
Notes:
1.
Caution:
The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to
and
for ratio
settings.
2. The memory bus speed is half of the DDR/DDR2 data rate, hence, half of the platform clock frequency.
Table 75. Memory Bus Clocking Specifications (MPC8545E)
Maximum Processor Core Frequency
Characteristic
800, 1000, 1200 MHz
Min
Memory bus clock speed
166
Max
200
MHz
1, 2
Unit
Notes
Notes:
1.
Caution:
The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to
and
for ratio
settings.
2. The memory bus speed is half of the DDR/DDR2 data rate, hence, half of the platform clock frequency.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
124
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
