Clocking
19.3 e500 Core PLL Ratio
Table 78 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This
ratio is determined by the binary value of LBCTL, LALE, and LGPL2 at power up, as shown in Table 78.
Table 78. e500 Core to CCB Clock Ratio
Binary Value of
LBCTL, LALE, LGPL2
Signals
Binary Value of
LBCTL, LALE, LGPL2
Signals
e500 core:CCB Clock Ratio
e500 core:CCB Clock Ratio
000
001
010
011
4:1
9:2
100
101
110
111
2:1
5:2
3:1
7:2
Reserved
3:2
19.4 Frequency Options
Table 79 shows the expected frequency values for the platform frequency when using a CCB clock to
SYSCLK ratio in comparison to the memory bus clock speed.
Table 79. Frequency Options of SYSCLK with Respect to Memory Bus Speeds
CCB to
SYSCLK (MHz)
SYSCLK Ratio
16.66
25
33.33
41.66
66.66
83
100
111
133.33
Platform/CCB Frequency (MHz)
2
3
333
445
400
533
4
333
400
500
5
333
400
533
415
500
6
8
333
375
417
500
9
10
12
16
20
333
400
533
400
500
333
Note: Due to errata Gen 13 the max sys clk frequency should not exceed 100 MHz if the core clk frequency is below
1200 MHz.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
126
Freescale Semiconductor
FREESCALE [ Freescale ]
