Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
8.4
eTSEC IEEE Std 1588™ AC Specifications
Figure 26 shows the data and command output timing diagram.
t
T1588CLKOUT
t
T1588CLKOUTH
TSEC_1588_CLK_OUT
t
T1588OV
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_OUT
Figure 26. eTSEC IEEE 1588 Output AC Timing
The output delay is count starting rising edge if t is non-inverting. Otherwise, it is count starting falling edge.
1
T1588CLKOUT
Figure 27 shows the data and command input timing diagram.
t
T1588CLK
t
T1588CLKH
TSEC_1588_CLK
TSEC_1588_TRIG_IN
t
T1588TRIGH
Figure 27. eTSEC IEEE 1588 Input AC timing
Table 41 provides the IEEE 1588 AC timing specifications.
Table 41. eTSEC IEEE 1588 AC Timing Specifications
At recommended operating conditions with LVDD/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Note
TSEC_1588_CLK clock period
TSEC_1588_CLK duty cycle
t
3.3
40
—
T
*9
ns
%
1
T1588CLK
TX_CLK
t
50
60
—
T1588CLKH
/t
T1588CLK
TSEC_1588_CLK peak-to-peak jitter
Rise time eTSEC_1588_CLK (20%–80%)
Fall time eTSEC_1588_CLK (80%–20%)
TSEC_1588_CLK_OUT clock period
t
—
1.0
1.0
—
—
—
—
250
2.0
2.0
—
ps
ns
ns
ns
—
—
—
—
T1588CLKINJ
t
T1588CLKINR
t
T1588CLKINF
t
2*t
T1588CLK
T1588CLKOUT
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
49
FREESCALE [ Freescale ]
