Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Table 24. FIFO Mode Transmit AC Timing Specification (continued)
At recommended operating conditions with LVDD/TVDD of 2.5V ± 5%
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Rise time TX_CLK (20%–80%)
t
—
—
—
—
—
—
0.75
0.75
—
ns
ns
ns
ns
FITR
Fall time TX_CLK (80%–20%)
t
FITF
FIFO data TXD[7:0], TX_ER, TX_EN setup time to GTX_CLK
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time
Notes:
t
2.0
0.5
FITDV
FITDX
t
3.0
1. The minimum cycle period (or maximum frequency) of the TX_CLK is dependent on the maximum platform frequency of the
speed bins the part belongs to as well as the FIFO mode under operation. Refer to Section 4.5, “Platform to eTSEC FIFO
Restrictions,” for more detailed description.
Table 25. FIFO Mode Receive AC Timing Specification
At recommended operating conditions with LVDD/TVDD of 2.5V ± 5%
Parameter/Condition
Symbol
Min
Typ
Max
Unit
1
RX_CLK clock period
t
5.3
45
—
8.0
50
—
—
—
—
—
100
55
ns
%
FIR
RX_CLK duty cycle
t
/t
FIRH FIR
RX_CLK peak-to-peak jitter
t
250
0.75
0.75
—
ps
ns
ns
ns
ns
FIRJ
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
t
—
FIRR
t
—
FIRF
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
t
1.5
0.5
FIRDV
FIRDX
t
—
1. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency of the
speed bins the part belongs to as well as the FIFO mode under operation. Refer to Section 4.5, “Platform to eTSEC FIFO
Restrictions,” for more detailed description.
Figure 7 and Figure 8 show the FIFO timing diagrams.
t
t
FITR
FITF
t
FIT
GTX_CLK
t
t
t
FITDX
FITH
FITDV
TXD[7:0]
TX_EN
TX_ER
Figure 7. FIFO Transmit AC Timing Diagram
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
31
FREESCALE [ Freescale ]
