Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Table 23. MII, GMII, RMII, RGMII, TBI, RTBI, and FIFO DC Electrical Characteristics (continued)
Parameters
Symbol
Min
Max
Unit
Notes
1, 2,3
Input high current
(V = LV , V = TV )
DD
I
—
10
μA
IH
IN
DD IN
3
Input low current
I
–15
—
μA
IL
(V = GND)
IN
Note:
1
2
3
LV supports eTSECs 1 and 2.
DD
TV supports eTSECs 3 and 4 or FEC.
DD
Note that the symbol V , in this case, represents the LV and TV symbols referenced in Table 1.
IN
IN
IN
8.2
FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing
Specifications
The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII and RTBI are presented in this
section.
8.2.1
FIFO AC Specifications
The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI
specifications, because they have similar performance and are described in a source-synchronous fashion
like FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and
source clock in GMII fashion.
When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the
relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK,
while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit
clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back on
the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is intended
that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a source-
synchronous timing reference. Typically, the clock edge that launched the data can be used, because the
clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is a
relationship between the maximum FIFO speed and the platform (CCB) frequency. For more information
see Section 4.5, “Platform to eTSEC FIFO Restrictions.”
Table 24 and Table 25 summarize the FIFO AC specifications.
Table 24. FIFO Mode Transmit AC Timing Specification
At recommended operating conditions with LVDD/TVDD of 2.5V ± 5%
Parameter/Condition
Symbol
Min
Typ
Max
Unit
1
TX_CLK, GTX_CLK clock period
t
5.3
45
—
8.0
50
—
100
55
ns
%
FIT
TX_CLK, GTX_CLK duty cycle
t
/t
FITH FIT
TX_CLK, GTX_CLK peak-to-peak jitter
t
250
ps
FITJ
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
30
FREESCALE [ Freescale ]
