DDR2 and DDR3 SDRAM Controller
Figure 6 provides the AC test load for the DDR2 and DDR3 Controller bus.
GV /2
Output
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 6. DDR2 and DDR3 Controller bus AC Test Load
6.2.3
DDR2 and DDR3 SDRAM Differential Timing Specifications
This section describes the DC and AC differential electrical specifications for the DDR2 and DDR3
SDRAM controller interface of the MPC8572E.
GVDD
V
V
TR
V
or V
OD
ID
V
IN
V
MP
V
or V
OX
IX
CP
GND
NOTE
VID specifies the input differential voltage |VTR -VCP| required for
switching, where VTR is the true input signal (such as MCK or MDQS) and
VCP is the complementary input signal (such as MCK or MDQS).
Table 18 provides the differential specifications for the MPC8572E differential signals MDQS/MDQS and
MCK/MCK when in DDR2 mode.
Table 18. DDR2 SDRAM Differential Electrical Characteristics
Parameter/Condition
DC Input Signal Voltage
Symbol
Min
Max
Unit
Notes
V
V
–0.3
GV + 0.3
V
—
—
—
—
—
—
—
IN
ID
DD
DC Differential Input Voltage
AC Differential Input Voltage
DC Differential Output Voltage
AC Differential Output Voltage
AC Differential Cross-point Voltage
Input Midpoint Voltage
—
—
—
—
mV
mV
mV
V
V
—
IDAC
V
—
OH
V
JEDEC: 0.5
JEDEC: GV + 0.6
OHAC
DD
V
—
—
—
—
mV
mV
IXAC
V
MP
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
26
FREESCALE [ Freescale ]
