DDR2 and DDR3 SDRAM Controller
Figure 3 shows the DDR2 and DDR3 SDRAM interface input timing diagram.
MCK[n]
MCK[n]
t
MCK
MDQS[n]
MDQ[x]
t
DISKEW
D0
D1
t
DISKEW
t
DISKEW
Figure 3. DDR2 and DDR3 SDRAM Interface Input Timing Diagram
6.2.2
DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications
Table 17 contains the output AC timing targets for the DDR2 and DDR3 SDRAM interface.
Table 17. DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications
At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3.
1
Parameter
MCK[n] cycle time
Symbol
Min
Max
Unit
Notes
t
2.5
5
ns
ns
2
3
MCK
ADDR/CMD output setup with respect to MCK
t
DDKHAS
DDKHAX
DDKHCS
800 MHz
0.917
1.10
1.48
1.95
—
—
—
—
667 MHz
533 MHz
400 MHz
ADDR/CMD output hold with respect to MCK
t
ns
3
800 MHz
0.917
1.10
1.48
1.95
—
—
—
—
667 MHz
533 MHz
400 MHz
MCS[n] output setup with respect to MCK
t
ns
3
800 MHz
667 MHz
533 MHz
0.917
1.10
1.48
—
—
—
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
22
FREESCALE [ Freescale ]
