DDR2 and DDR3 SDRAM Controller
Table 17. DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications (continued)
At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3.
1
Parameter
Symbol
Min
Max
Unit
Notes
<= 667 MHz
t
–0.6
0.6
ns
6
DDKHME
Note:
1. The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. Output hold time can
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went
invalid (AX or DX). For example, t symbolizes DDR timing (DD) for the time t memory clock reference
DDKHAS
MCK
(K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, t
symbolizes DDR
DDKLDX
timing (DD) for the time t
output hold time.
memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data
MCK
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that t
follows the symbol conventions described in note 1. For example, t
describes the DDR
DDKHMH
DDKHMH
timing (DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
can be
DDKHMH
modified through control of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This
typically be set to the same delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in
the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8572E
PowerQUICC™ III Integrated Host Processor Family Reference Manual for a description and understanding of the
timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ),
ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the
microprocessor.
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t
the symbol conventions described in note 1.
follows
DDKHMP
NOTE
For the ADDR/CMD setup and hold specifications in Table 17, it is
assumed that the clock control register is set to adjust the memory clocks by
1/2 applied cycle.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
24
Freescale Semiconductor
FREESCALE [ Freescale ]
