DDR2 and DDR3 SDRAM Controller
Figure 4 shows the DDR2 and DDR3 SDRAM Interface output timing for the MCK to MDQS skew
measurement (tDDKHMH).
MCK[n]
MCK[n]
tMCK
t
s
DDKHMHmax) = 0.6 ns or 0.375 n
MDQS
t
DDKHMH(min) = –0.6 ns or -0.375 ns
MDQS
Figure 4. Timing Diagram for tDDKHMH
Figure 5 shows the DDR2 and DDR3 SDRAM Interface output timing diagram.
MCK[n]
MCK[n]
t
MCK
t
,t
DDKHAS DDKHCS
t
,t
DDKHAX DDKHCX
ADDR/CMD
Write A0
NOOP
t
DDKHMP
t
DDKHMH
MDQS[n]
MDQ[x]
t
DDKHME
t
DDKHDS
t
DDKLDS
D0
D1
t
DDKLDX
t
DDKHDX
Figure 5. DDR2 and DDR3 SDRAM Interface Output Timing Diagram
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
25