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MPC8572ELVTAULD 参数 Datasheet PDF下载

MPC8572ELVTAULD图片预览
型号: MPC8572ELVTAULD
PDF下载: 下载PDF文件 查看货源
内容描述: MPC8572E的PowerQUICC III集成处理器硬件规格 [MPC8572E PowerQUICC III Integrated Processor Hardware Specifications]
分类和应用: PC
文件页数/大小: 140 页 / 1412 K
品牌: FREESCALE [ Freescale ]
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DDR2 and DDR3 SDRAM Controller  
AC specifications of the DDR3 memory to be used are compliant to both JEDEC specifications as well as  
the specifications and requirements described in this MPC8572E hardware specifications document.  
6.2.1  
DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications  
Table 14, Table 15, and Table 16 provide the input AC timing specifications for the DDR controller when  
interfacing to DDR2 and DDR3 SDRAM.  
Table 14. DDR2 SDRAM Interface Input AC Timing Specifications for 1.8-V Interface  
At recommended operating conditions with GVDD of 1.8 V ± 5%  
Parameter  
Symbol  
Min  
Max  
Unit  
Notes  
AC input low voltage  
>=667 MHz  
V
MV  
MV  
n – 0.20  
V
ILAC  
REF  
<= 533 MHz  
>=667 MHz  
<= 533 MHz  
n – 0.25  
REF  
AC input high voltage  
V
MV  
MV  
n + 0.20  
V
IHAC  
REF  
REF  
n + 0.25  
Table 15. DDR3 SDRAM Interface Input AC Timing Specifications for 1.5-V Interface  
At recommended operating conditions with GVDD of 1.5 V ± 5%. DDR3 data rate is between 606 MHz and 800 MHz.  
Parameter  
Symbol  
Min  
Max  
Unit  
Notes  
AC input low voltage  
AC input high voltage  
V
MV  
n – 0.175  
V
V
ILAC  
REF  
V
MV  
n + 0.175  
REF  
IHAC  
Table 16. DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications  
At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3.  
Parameter  
Symbol  
Min  
Max  
Unit  
Notes  
Controller Skew for MDQS—MDQ/MECC  
t
ps  
1, 2  
CISKEW  
800 MHz  
667 MHz  
533 MHz  
400 MHz  
Note:  
–200  
–240  
–300  
–365  
200  
240  
300  
365  
1. t  
represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding  
CISKEW  
bit that is captured with MDQS[n]. This should be subtracted from the total timing budget.  
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be  
determined by the following equation: tDISKEW =+/–(T/4 – abs(tCISKEW)) where T is the clock period and  
abs(tCISKEW) is the absolute value of tCISKEW.  
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4  
Freescale Semiconductor  
21  
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