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MPC8572ELVTAULD 参数 Datasheet PDF下载

MPC8572ELVTAULD图片预览
型号: MPC8572ELVTAULD
PDF下载: 下载PDF文件 查看货源
内容描述: MPC8572E的PowerQUICC III集成处理器硬件规格 [MPC8572E PowerQUICC III Integrated Processor Hardware Specifications]
分类和应用: PC
文件页数/大小: 140 页 / 1412 K
品牌: FREESCALE [ Freescale ]
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DDR2 and DDR3 SDRAM Controller  
Table 11. DDR3 SDRAM Interface DC Electrical Characteristics for GV (typ) = 1.5 V (continued)  
DD  
Parameter/Condition  
Symbol  
Min  
Typical  
Max  
Unit  
Output leakage current  
Notes:  
I
–50  
50  
μA  
3
OZ  
1. GV is expected to be within 50 mV of the DRAM GV at all times.  
DD  
DD  
2. MV  
n is expected to be equal to 0.5 × GV , and to track GV DC variations as measured at the receiver.  
REF  
DD DD  
n may not exceed ±1% of the DC value.  
Peak-to-peak noise on MV  
REF  
3. Output leakage is measured with all outputs disabled, 0 V VOUT GV  
.
DD  
Table 12 provides the DDR SDRAM Controller interface capacitance for DDR2 and DDR3.  
Table 12. DDR2 and DDR3 SDRAM Interface Capacitance for GV (typ)=1.8 V and 1.5 V  
DD  
Parameter/Condition  
Symbol  
Min  
Typical  
Max  
Unit  
Input/output capacitance: DQ, DQS, DQS  
Delta input/output capacitance: DQ, DQS, DQS  
Note:  
C
6
8
pF  
pF  
1, 2  
1, 2  
IO  
C
0.5  
DIO  
1. This parameter is sampled. GV = 1.8 V ± 0.090 V (for DDR2), f = 1 MHz, T = 25°C, V  
= GV /2, V  
DD OUT  
DD  
A
OUT  
(peak-to-peak) = 0.2 V.  
2. This parameter is sampled. GV = 1.5 V ± 0.075 V (for DDR3), f = 1 MHz, T = 25°C, V  
= GV /2, V  
OUT  
DD  
A
OUT  
DD  
(peak-to-peak) = 0.175 V.  
Table 13 provides the current draw characteristics for MV n.  
REF  
Table 13. Current Draw Characteristics for MV  
n
REF  
Parameter / Condition  
Symbol  
Min  
Max  
Unit  
Note  
Current draw for MV  
n
DDR2 SDRAM  
DDR3 SDRAM  
I
n
1500  
1250  
μA  
1
REF  
MVREF  
1. The voltage regulator for MV  
n must be able to supply up to 1500 μA or 1250 uA current for DDR2 or DDR3 respectively.  
REF  
6.2  
DDR2 and DDR3 SDRAM Interface AC Electrical Characteristics  
This section provides the AC electrical characteristics for the DDR SDRAM Controller interface. The  
DDR controller supports both DDR2 and DDR3 memories. Note that although the minimum data rate for  
most off-the-shelf DDR3 DIMMs available is 800 MHz, JEDEC specification does allow the DDR3 to run  
at the data rate as low as 606 MHz. Unless otherwise specified, the AC timing specifications described in  
this section for DDR3 is applicable for data rate between 606 MHz and 800 MHz, as long as the DC and  
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4  
20  
Freescale Semiconductor  
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