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MPC8572ELVTAULD 参数 Datasheet PDF下载

MPC8572ELVTAULD图片预览
型号: MPC8572ELVTAULD
PDF下载: 下载PDF文件 查看货源
内容描述: MPC8572E的PowerQUICC III集成处理器硬件规格 [MPC8572E PowerQUICC III Integrated Processor Hardware Specifications]
分类和应用: PC
文件页数/大小: 140 页 / 1412 K
品牌: FREESCALE [ Freescale ]
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DDR2 and DDR3 SDRAM Controller  
6 DDR2 and DDR3 SDRAM Controller  
This section describes the DC and AC electrical specifications for the DDR2 and DDR3 SDRAM  
controller interface of the MPC8572E. Note that the required GV (typ) voltage is 1.8Vor 1.5V when  
DD  
interfacing to DDR2 or DDR3 SDRAM respectively.  
6.1  
DDR2 and DDR3 SDRAM Interface DC Electrical Characteristics  
Table 10 provides the recommended operating conditions for the DDR SDRAM Controller of the  
MPC8572E when interfacing to DDR2 SDRAM.  
Table 10. DDR2 SDRAM Interface DC Electrical Characteristics for GV (typ) = 1.8 V  
DD  
Parameter/Condition  
I/O supply voltage  
Symbol  
GV  
Min  
Max  
Unit  
Notes  
1.71  
1.89  
V
V
1
2
DD  
I/O reference voltage  
I/O termination voltage  
Input high voltage  
MV  
n
0.49 × GV  
0.51 × GV  
DD  
REF  
DD  
V
MV  
n – 0.04  
MV n + 0.04  
REF  
V
3
TT  
REF  
V
MV  
n + 0.125  
GV + 0.3  
V
4
IH  
REF  
DD  
Input low voltage  
V
–0.3  
–50  
MV  
n – 0.125  
REF  
V
IL  
Output leakage current  
I
50  
μA  
mA  
mA  
OZ  
OH  
Output high current (V  
= 1.420 V)  
I
–13.4  
13.4  
OUT  
Output low current (V  
= 0.280 V)  
I
OL  
OUT  
Notes:  
1. GV is expected to be within 50 mV of the DRAM GV at all times.  
DD  
DD  
2. MV  
n is expected to be equal to 0.5 × GV , and to track GV DC variations as measured at the receiver.  
REF  
DD DD  
n may not exceed ±2% of the DC value.  
Peak-to-peak noise on MV  
REF  
3. V is not applied directly to the device. It is the supply to that far end signal termination is made and is expected to be  
TT  
equal to MV  
n. This rail should track variations in the DC level of MV  
n.  
REF  
REF  
4. Output leakage is measured with all outputs disabled, 0 V VOUT GV  
.
DD  
Table 11 provides the recommended operating conditions for the DDR SDRAM Controller of the  
MPC8572E when interfacing to DDR3 SDRAM.  
Table 11. DDR3 SDRAM Interface DC Electrical Characteristics for GV (typ) = 1.5 V  
DD  
Parameter/Condition  
I/O supply voltage  
Symbol  
GV  
Min  
Typical  
Max  
Unit  
1.425  
1.575  
V
V
V
V
1
2
DD  
I/O reference voltage  
Input high voltage  
Input low voltage  
MV  
n
0.49 × GV  
0.51 × GV  
DD  
REF  
DD  
V
MV  
n + 0.100  
GV  
DD  
IH  
REF  
V
GND  
MV  
n – 0.100  
REF  
IL  
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4  
Freescale Semiconductor  
19  
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