Input Clocks
Table 6. EC_GTX_CLK125 AC Timing Specifications (continued)
At recommended operating conditions with LVDD/TVDD of 3.3V ± 5% or 2.5V ± 5% (continued)
Parameter/Condition
Symbol
/t
Min
Typical
Max
Unit
Notes
EC_GTX_CLK125 duty cycle
t
—
%
2, 3
G125H G125
GMII, TBI
1000Base-T for RGMII, RTBI
45
47
55
53
Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5V and 2.0V for L/TV =2.5V, and from 0.6V and 2.7V
DD
for L/TV =3.3V.
DD
2. Timing is guaranteed by design and characterization.
3. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation.
EC_GTX_CLK125 duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle
generated by the TSECn_GTX_CLK. See Section 8.2.6, “RGMII and RTBI AC Timing Specifications,” for duty cycle
for 10Base-T and 100Base-T reference clock.
4.4
DDR Clock Timing
Table 7 provides the DDR clock (DDRCLK) AC timing specifications for the MPC8572E.
Table 7. DDRCLK AC Timing Specifications
At recommended operating conditions with OVDD of 3.3V ± 5%.
Parameter/Condition
DDRCLK frequency
Symbol
Min
Typical
Max
Unit
Notes
f
t
66
10.0
0.6
40
—
—
100
15.15
1.2
MHz
ns
1
—
DDRCLK
DDRCLK
DDRCLK cycle time
DDRCLK rise and fall time
DDRCLK duty cycle
DDRCLK jitter
t
, t
1.0
—
ns
2
KH KL
t
/t
60
%
3
KHK DDRCLK
—
—
—
+/– 150
ps
4, 5, 6
Notes:
1. Caution: The DDR complex clock to DDRCLK ratio settings must be chosen such that the resulting DDR complex
clock frequency does not exceed the maximum or minimum operating frequencies. Refer to Section 19.4,
“DDR/DDRCLK PLL Ratio,” for ratio settings.
2. Rise and fall times for DDRCLK are measured at 0.6 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The DDRCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track DDRCLK drivers with the specified jitter.
6. For spread spectrum clocking, guidelines are +0% to –1% down spread at a modulation rate between 20 kHz and
60 kHz on DDRCLK.
4.5
Platform to eTSEC FIFO Restrictions
Note the following eTSEC FIFO mode maximum speed restrictions based on platform (CCB) frequency.
For FIFO GMII modes (both 8-bit and 16-bit) and 16-bit Encoded FIFO mode:
FIFO TX/RX clock frequency <= platform clock (CCB) frequency/4.2
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
17
FREESCALE [ Freescale ]
