Electrical Characteristics
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8572E.
T/B/G/L/OV + 20%
DD
T/B/G/L/OV + 5%
DD
T/B/G/L/OV
VIH
DD
GND
GND – 0.3 V
VIL
GND – 0.7 V
Not to Exceed 10%
of t
1
CLOCK
Note:
t
refers to the clock period associated with the respective interface:
CLOCK
2
For I C and JTAG, t
references SYSCLK.
CLOCK
For DDR, t
references MCLK.
CLOCK
For eTSEC, t
references EC_GTX_CLK125.
CLOCK
For eLBC, t
references LCLK.
CLOCK
Figure 2. Overshoot/Undershoot Voltage for TV /BV /GV /LV /OV
DD
DD
DD
DD
DD
The core voltage must always be provided at nominal 1.1 V. (See Table 2 for actual recommended core
voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must
be provided at the voltages shown in Table 2. The input voltage threshold scales with respect to the
associated I/O supply voltage. TV , BV , OV and LV based receivers are simple CMOS I/O
DD
DD
DD
DD
circuits and satisfy appropriate LVCMOS type specifications. The DDR2 and DDR3 SDRAM interface
uses differential receivers referenced by the externally supplied MV n signal (nominally set to GV /2)
REF
DD
as is appropriate for the SSTL_1.8 electrical signaling standard for DDR2 or 1.5-V electrical signaling for
DDR3. The DDR DQS receivers cannot be operated in single-ended fashion. The complement signal must
be properly driven and cannot be grounded.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
13
FREESCALE [ Freescale ]
