Electrical Characteristics
2.1.3
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
Table 3. Output Drive Capability
Programmable
Supply
Driver Type
Output Impedance
Notes
Voltage
(Ω)
Local bus interface utilities signals
25
35
BV = 3.3 V
1
DD
BV = 2.5 V
DD
45(default)
45(default)
125
BV = 3.3 V
DD
BV = 2.5 V
DD
BV = 1.8 V
DD
DDR2 signal
DDR3 signal
18
GV = 1.8 V
2
2
DD
36 (half strength mode)
20
GV = 1.5 V
DD
40 (half strength mode)
eTSEC/10/100 signals
45
45
L/TV = 2.5/3.3 V
—
—
—
DD
DUART, system control, JTAG
OV = 3.3 V
DD
I2C
150
OV = 3.3 V
DD
Notes:
1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.
2. The drive strength of the DDR2 or DDR3 interface in half-strength mode is at T = 105°C and at GV (min).
j
DD
2.2
Power Sequencing
The MPC8572E requires its power rails to be applied in a specific sequence to ensure proper device
operation. These requirements are as follows for power up:
1. V , AV _n, BV , LV , OV , SV
and SV
, TV , XV
and
DD
DD
DD
DD
DD
DD_SRDS1
DD_SRDS2
DD
DD_SRDS1
XV
DD_SRDS2
DD
2. GV
All supplies must be at their stable values within 50 ms.
Items on the same line have no ordering requirement with respect to one another. Items on separate lines
must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before
the voltage rails on the current step reach 10% of theirs.
To guarantee MCKE low during power-on reset, the above sequencing for GV is required. If there is no
DD
concern about any of the DDR signals being in an indeterminate state during power-on reset, then the
sequencing for GV is not required.
DD
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
14
FREESCALE [ Freescale ]
