Power Characteristics
NOTE
From a system standpoint, if any of the I/O power supplies ramp prior to the
VDD core supply, the I/Os associated with that I/O supply may drive a logic
one or zero during power-on reset, and extra current may be drawn by the
device.
3 Power Characteristics
The estimated typical power dissipation for the core complex bus (CCB) versus the core frequency for this
family of PowerQUICC III devices is shown in Table 4.
1
Table 4. MPC8572E Power Dissipation
2
3
4
CCB Frequency
Core Frequency
Typical-65
Typical-105
Maximum
Unit
533
533
533
600
1067
1200
1333
1500
12.3
12.3
16.3
17.3
17.8
17.8
22.8
23.9
18.5
18.5
24.5
25.9
W
W
W
W
Notes:
1
2
3
4
This reflects the MPC8572E power dissipation excluding the power dissipation from B/G/L/O/T/XV rails.
DD
Typical-65 is based on V = 1.1 V, T = 65 °C, running Dhrystone.
DD
j
Typical-105 is based on V = 1.1 V, T = 105 °C, running Dhrystone.
DD
j
Maximum is based on V = 1.1 V, T = 105 °C, running a smoke test.
DD
j
4 Input Clocks
4.1
System Clock Timing
Table 5 provides the system clock (SYSCLK) AC timing specifications for the MPC8572E.
Table 5. SYSCLK AC Timing Specifications
At recommended operating conditions with OVDD of 3.3V ± 5%.
Parameter/Condition
SYSCLK frequency
Symbol
Min
Typical
Max
Unit
Notes
f
t
33
7.5
0.6
40
—
—
133
30.3
1.2
MHz
ns
1
—
2
SYSCLK
SYSCLK cycle time
SYSCLK
SYSCLK rise and fall time
SYSCLK duty cycle
t
, t
1.0
—
ns
KH KL
t
/t
60
%
3
KHK SYSCLK
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
15
FREESCALE [ Freescale ]
