Overview
— 256-byte maximum payload size
— Virtual channel 0 only
— Full 64-bit decode with 36-bit wide windows
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Pin multiplexing for the high-speed I/O interfaces supports one of the following configurations:
— Single x8/x4/x2/x1 PCI Express
— Dual x4/x2/x1 PCI Express
— Single x4/x2/x1 PCI Express and dual x2/x1 PCI Express
— Single 1x/4x Serial RapidIO and single x4/x2/x1 PCI Express
Power management
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— Supports power saving modes: doze, nap, and sleep
— Employs dynamic power management, that automatically minimizes power consumption of
blocks when they are idle
System performance monitor
— Supports eight 32-bit counters that count the occurrence of selected events
— Ability to count up to 512 counter-specific events
— Supports 64 reference events that can be counted on any of the eight counters
— Supports duration and quantity threshold counting
— Permits counting of burst events with a programmable time between bursts
— Triggering and chaining capability
— Ability to generate an interrupt on overflow
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System access port
— Uses JTAG interface and a TAP controller to access entire system memory map
— Supports 32-bit accesses to configuration registers
— Supports cache-line burst accesses to main memory
— Supports large block (4-Kbyte) uploads and downloads
— Supports continuous bit streaming of entire block for fast upload and download
IEEE Std 1149.1™ compatible, JTAG boundary scan
1023 FC-PBGA package
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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
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FREESCALE [ Freescale ]
