Document Revision History
Table 61. Document Revision History (continued)
Substantive Change(s)
Rev. No.
3.2
Updated Table 1 and Table 2 with 1.0 GHz device parameter requirements.
Added Section 2.1.2, “Power Sequencing”.
Updated Table 4 with Maximum power data.
Updated Table 4 and Table 5 with 1 GHz speed grade information.
Updated Table 6 with corrected typical I/O power numbers.
Updated Table 7 Note 2 lower voltage measurement point.
Replaced Table 7 Note 5 with spread spectrum clocking guidelines.
Added to Table 8 rise and fall time information.
Added Section 4.4, “Real Time Clock Timing”.
Added precharge information to Section 6.2.2, “DDR SDRAM Output AC Timing Specifications”.
Updated Table 20 minimum and maximum baud rates.
Removed VIL and VIH references from Table 23, Table 24, Table 25, and Table 26.
Added reference level note to Table 23, Table 24, Table 25, Table 26, Table 27, Table 28, and Table 29.
Updated TXD references to TCG in Section 8.2.3.1, “TBI Transmit AC Timing Specifications”.
Updated PMA_RX_CLK references to RX_CLK in Section 8.2.3.2, “TBI Receive AC Timing Specifications”.
Updated tTTKHDX value in Table 27.
Updated RXD references to RCG in Section 8.2.3.2, “TBI Receive AC Timing Specifications”.
Updated Table 29 Note 2.
Removed VIL and VIH references from Table 31, and Table 32.
Added reference level note to Table 31, and Table 32.
Corrected Figure 14 and Figure 15.
Corrected Table 34 fMDC and tMDC to reflect the correct minimum operating frequency.
Updated Table 34 tMDKHDV and tMDKHDX values for clarification.
Added tLBKHKT and updated Note 2 in Table 37.
Corrected LGTA timing references in Figure 18.
Updated Figure 19, Figure 21, and Figure 23.
Updated Figure 43.
Clarified Table 53 Note 5.
Updated Table 54 and Table 55 with 1 GHz information.
Added heat sink removal discussion to Section 16.2.3, “Thermal Interface Materials”.
Corrected and added 1 GHz part number to Table 62.
3.1
Updated Table 4 and Table 5.
Added Table 6.
Added MCK duty cycle to Table 16.
Updated fMDC, tMDC, tMDKHDV, and tMDKHDX parameters in Table 34.
Added LALE to tLBKHOV3 parameter in Table 36 and Table 37, and updated Figure 18 and Figure 19.
Corrected active level designations of some of the pins in Table 53.
Updated Table 62.
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
97
FREESCALE [ Freescale ]
