Document Revision History
18 Document Revision History
Table 61 provides a revision history for this hardware specification.
Table 61. Document Revision History
Rev. No.
Substantive Change(s)
Updated Note in Section 2.1.2, “Power Sequencing.”
4
Updated back page information.
3.5
3.4
Updated Section 2.1.2, “Power Sequencing.”
Replaced Section 17.8, “JTAG Configuration Signals.”
Corrected MVREF Max Value in Table 1.
Corrected MVREF Max Value in Table 2.
Added new revision level information to Table 62
3.3
Updated MVREF Max Value in Table 1.
Removed Figure 3.
In Table 4, replaced TBD with power numbers and added footnote.
Updated specs and footnotes in Table 8.
Corrected max number for MVREF in Table 13.
Changed parameter “Clock cycle duration” to “Clock period” in Table 29.
Added note 4 to tLBKHOV1 and removed LALE reference from tLBKHOV3 in Table 36 and Table 37.
Updated LALE signal in Figure 18 and Figure 19.
Modified Figure 22.
Modified Figure 54.
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
96
Freescale Semiconductor
FREESCALE [ Freescale ]
