Document Revision History
Table 61. Document Revision History (continued)
Rev. No.
2.0
Substantive Change(s)
Section 1.1—Updated features list to coincide with latest version of the reference manual
and
of SYSCLK to OV
IN
of notes 1 and 2
of note 1
Section 4—New
of I
VREF
Removed Figure 4 DDR SRAM Input TIming Diagram
maximum values for t
DISKEW
MSYNC_OUT to tMCKSKEW2
Section 6.2.1—Removed Figure 4, “DDR SDRAM Input Timing Diagram”
Section 8.1—Removed references to 2.5 V from first paragraph
and
“conditions” for I
IH
and I
IL
of min and max for GTX_CLK125 reference clock duty cycle
—Addition of min and max for GTX_CLK125 reference clock duty cycle
of min and max for GTX_CLK125 reference clock duty cycle
min and conditions; I
IH
and I
IL
conditions
and max for t
MTXR
and t
MTXF
and max for t
MRXR
and t
MRXF
and
LSYNC_IN to Internal clock at top of each figure
row for tLBKHOX3
(AC timing of PCI-X at 66 MHz)
of note 19
of jumper and note at top of diagram
Changed max bus freq for 667 core to 166
Section 16.2.1—Modified first paragraph
thermal resistance data
Section 16.2.4.2—Modified first and second paragraphs
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
99
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
