RapidIO
shows the DC driver signal levels.
V
OA
R
TERM
100
Ω
(no m)
V
OB
V
OD
= V
OA
– V
OB
454 mV
V
247 mV V
OHD
V
OLCM
–247 mV
V
OLD
–454 mV
Differential Specifications
Common-Mode Specifications
(c)
0
1.125 V
(a)
V
OSCM
= (V
OA
+ V
OB
)/2
V
OHCM
1.375 V
ΔV
OS
V
V
OD
= V
OA
– V
OB
–V +
ΔV
OD
–V
–V –
ΔV
OD
(b)
Note:
V
OA
refers to voltage at output A; V
OB
refers to voltage at output B.
Figure 34. DC Driver Signal Levels
13.2 RapidIO AC Electrical Specifications
This section contains the AC electrical specifications for a RapidIO 8/16 LP-LVDS device. The interface
defined is a parallel differential low-power high-speed signal interface. Note that the source of the transmit
clock on the RapidIO interface is
dependent o
n the settings of the LGPL[0:1] signals at reset. Note that the
default setting makes the core complex bus (CCB) clock the source of the transmit clock. See Chapter 4
of the Reference Manual for more details on reset configuration settings.
13.3 RapidIO Concepts and Definitions
This section specifies signals using differential voltages.
shows how the signals are defined. The
figure shows waveforms for either a transmitter output (TD and TD) or a receiver input (RD and RD). Each
signal swings between A volts and B volts where A > B. Using these waveforms, the definitions are as
follows:
• The transmitter output and receiver input signals TD, TD, RD, and RD each have a peak-to-peak
swing of A-B volts.
• The differential output signal of the transmitter, V
OD
, is defined as V
TD
– V
TD
.
• The differential input signal of the receiver, V
ID
, is defined as V
RD
– V
RD
.
• The differential output signal of the transmitter or input signal of the receiver, ranges from
A – B volts to – (A – B) volts.
• The peak differential signal of the transmitter output or receiver input, is A – B volts.
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
56
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
