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MPC8540CPX667JC 参数 Datasheet PDF下载

MPC8540CPX667JC图片预览
型号: MPC8540CPX667JC
PDF下载: 下载PDF文件 查看货源
内容描述: 集成处理器的硬件规格 [Integrated Processor Hardware Specifications]
分类和应用: 外围集成电路时钟
文件页数/大小: 104 页 / 1354 K
品牌: FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
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RapidIO
Table 49. RapidIO Driver AC Timing Specifications—1 Gbps Data Rate
Range
Characteristic
Symbol
Min
Differential output high voltage
Differential output low voltage
Duty cycle
V
OD
rise time, 20%–80% of peak to peak
differential signal swing
V
OD
fall time, 20%–80% of peak to peak
differential signal swing
Data valid
Skew of any two data outputs
Skew of single data outputs to associated clock
V
OHD
V
OLD
DC
t
FALL
t
RISE
DV
t
DPAIR
t
SKEW,PAIR
200
–540
48
100
100
575
–100
Max
540
–200
52
100
100
mV
mV
%
ps
ps
ps
ps
ps
1
1
2, 6
3, 6
6
6
4, 6
5, 6
Unit
Notes
Notes:
1.See
2.Requires ±100 ppm long term frequency stability.
3.Measured at V
OD
= 0 V.
4.Measured using the RapidIO transmit mask shown in
5.See
6.Guaranteed by design.
The compliance of driver output signals TD[0:15] and TFRAME with their minimum data valid window
(DV) specification shall be determined by generating an eye pattern for each of the data signals and
comparing the eye pattern of each data signal with the RapidIO transmit mask shown in
The
value of X2 used to construct the mask shall be (1 – DV
min
)/2. A signal is compliant with the data valid
window specification if the transmit mask can be positioned on the signal’s eye pattern such that the eye
pattern falls entirely within the unshaded portion of the mask.
V
OHDmax
V
OHDmin
V
OD
(mV)
0
V
OLDmax
DV
V
OLDmin
0
X2
1–X2
1
Time (UI)
Figure 37. RapidIO Transmit Mask
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
60
Freescale Semiconductor