RapidIO
Table 44. PCI-X AC Timing Specifications at 133 MHz (continued)
Parameter
HRESET to PCI-X initialization pattern hold time
Symbol
t
PCRHIX
Min
0
Max
50
Unit
ns
Notes
6, 12
Notes:
1.See the timing measurement conditions in the
PCI-X 1.0a Specification.
2.Minimum times are measured at the package pin (not the test point). Maximum times are measured with the test
point and load circuit.
3.Setup time for point-to-point signals applies to REQ and GNT only. All other signals are bused.
4.For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
5.Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same
time.
6.Maximum value is also limited by delay to the first transaction (time for HRESET high to first configuration access,
t
PCRHFV
). The PCI-X initialization pattern control signals after the rising edge of HRESET must be negated no
later than two clocks before the first FRAME and must be floated no later than one clock before FRAME is
asserted.
7.A PCI-X device is permitted to have the minimum values shown for t
PCKHOV
and t
CYC
only in PCI-X mode. In
conventional mode, the device must meet the requirements specified in PCI 2.2 for the appropriate clock
frequency.
8.Device must meet this specification independent of how many outputs switch simultaneously.
9.The timing parameter t
PCIVKH
is a minimum of 1.4 ns rather than the minimum of 1.2 ns in the
PCI-X 1.0a
Specification.
10.The timing parameter t
PCRHFV
is a minimum of 10 clocks rather than the minimum of 5 clocks in the
PCI-X 1.0a
Specification.
11.Guaranteed by characterization.
12.Guaranteed by design.
13 RapidIO
This section describes the DC and AC electrical specifications for the RapidIO interface of the MPC8540.
13.1 RapidIO DC Electrical Characteristics
RapidIO driver and receiver DC electrical characteristics are provided in
and
respectively.
Table 45. RapidIO 8/16 LP-LVDS Driver DC Electrical Characteristics
At recommended operating conditions with OV
DD
of 3.3 V ± 5%.
Characteristic
Differential output high voltage
Differential output low voltage
Differential offset voltage
Output high common mode voltage
Output low common mode voltage
Symbol
V
OHD
V
OLD
ΔV
OSD
V
OHCM
V
OLCM
Min
247
–454
—
1.125
1.125
Max
454
–247
50
1.375
1.375
Unit
mV
mV
mV
V
V
Notes
1, 2
1, 2
1,3
1, 4
1, 5
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
54
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
