Clocking
3
4
The DDR data rate is 2× the DDR memory bus frequency.
The local bus frequency is ½, ¼, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1× or 2× the
csb_clk frequency (depending on RCWL[LBIUCM]).
19.1 System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 60 shows the multiplication factor
encodings for the system PLL.
Table 60. System PLL Multiplication Factors
RCWL[SPMF]
System PLL Multiplication Factor
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
× 16
Reserved
× 2
× 3
× 4
× 5
× 6
× 7
× 8
× 9
× 10
× 11
× 12
× 13
× 14
× 15
As described in Section 19, “Clocking,” the LBIUCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 61
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
Freescale Semiconductor
79
FREESCALE [ Freescale ]
