Clocking
19.3 Suggested PLL Configurations
Table 64 shows suggested PLL configurations for 33 and 66 MHz input clocks.
Table 64. Suggested PLL Configurations
RCWL
400 MHz Device
533 MHz Device
667 MHz Device
Input
Input
Input
Clock
Freq
Ref
CSB
Freq
(MHz)
Core
Freq
(MHz)
CSB
Freq
(MHz)
Core
Freq
(MHz)
CSB
Freq
(MHz)
Core
Freq
(MHz)
No.1
CORE
PLL
Clock
Freq
Clock
Freq
SPMF
(MHz)2
(MHz)2
(MHz)2
33 MHz CLKIN/PCI_CLK Options
922
723
604
624
803
823
903
923
704
724
A03
804
705
606
904
805
A04
1001
0111
0110
0110
1000
1000
1001
1001
0111
0111
1010
1000
0111
0110
1001
1000
1010
0100010
0100011
0000100
0100100
0000011
0100011
0000011
0100011
0000011
0100011
0000011
0000100
0000101
0000110
0000100
0000101
0000100
—
33
33
33
33
33
—
233
200
200
266
266
—
—
—
33
33
33
33
33
33
33
33
33
33
33
—
233
200
200
266
266
300
300
233
233
333
266
—
f300
350
400
400
400
400
450
450
466
466
500
533
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
300
233
200
200
266
266
300
300
233
233
333
266
233
200
300
266
333
300
350
400
400
400
400
450
450
466
466
500
533
583
600
600
667
667
350
400
400
400
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
66 MHz CLKIN/PCI_CLK Options
304
324
403
423
305
503
404
0011
0011
0100
0100
0011
0101
0100
0000100
0100100
0000011
0100011
0000101
0000011
0000100
66
66
66
66
200
200
266
266
—
400
400
400
400
66
66
66
66
66
66
66
200
200
266
266
200
333
266
400
400
400
400
500
500
533
66
66
66
66
66
66
66
200
200
266
266
200
333
266
400
400
400
400
500
500
533
—
—
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
Freescale Semiconductor
83
FREESCALE [ Freescale ]
