Clocking
VCO divider must be set properly so that the core VCO frequency is in the
range of 800–1800 MHz.
Table 63. e300 Core PLL Configuration
RCWL[COREPLL]
core_clk : csb_clk Ratio
VCO Divider1
0–1
2–5
6
nn
0000
n
PLL bypassed
PLL bypassed
(PLL off, csb_clk clocks core directly) (PLL off, csb_clk clocks core directly)
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
0001
0001
0001
0001
0001
0001
0001
0001
0010
0010
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1:1
1:1
2
4
8
8
2
4
8
8
2
4
8
8
2
4
8
8
2
4
8
8
1:1
1:1
1.5:1
1.5:1
1.5:1
1.5:1
2:1
2:1
2:1
2:1
2.5:1
2.5:1
2.5:1
2.5:1
3:1
3:1
3:1
3:1
1
Core VCO frequency = core frequency × VCO divider. The VCO divider must be set properly so that the core VCO frequency
is in the range of 800–1800 MHz.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
82
Freescale Semiconductor
FREESCALE [ Freescale ]
