Clocking
19 Clocking
Figure 42 shows the internal distribution of the clocks.
e300 Core
Core PLL
core_clk
csb_clk
To DDR
Memory
6
6
DDR
Controller
DDR
Memory
Device
MCK[0:5]
MCK[0:5]
Clock
Div
/2
ddr_clk
Clock
Unit
System PLL
lbiu_clk
/n
LCLK[0:2]
To Local Bus
Memory
Local Bus
Memory
Device
LBIU
DLL
LSYNC_OUT
LSYNC_IN
Controller
csb_clk to Rest
of the Device
PCI_CLK/
PCI_SYNC_IN
CFG_CLKIN_DIV
CLKIN
PCI_SYNC_OUT
PCI Clock
Divider
5
PCI_CLK_OUT[0:4]
Figure 42. MPC8347EA Clock Subsystem
The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device
is configured in PCI host or PCI agent mode. When the MPC8347EA is configured as a PCI host device,
CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the multiplexors for
PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether
CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] parameters select
whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the MPC8347EA to function. When the
device is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN signal
should be tied to GND.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
76
Freescale Semiconductor
FREESCALE [ Freescale ]
